lc7874e Sanyo Semiconductor Corporation, lc7874e Datasheet - Page 10

• Manufacturer Part Number: lc7874e
• Description: Cd Graphics Decorder
• Manufacturer: Sanyo Semiconductor Corporation

Pin Functions
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
3
4
5
6
7
8
9
Pin Symbol
CSYNC
BLANK
CDGM
MUTE
SBCK
SBSY
SFSY
V
CE1
CAS
RAS
DB0
DB1
DB2
DB3
V
PW
WE
CE
DO
CB
OE
S1
S2
CL
A0
A1
A2
A3
A4
A5
A6
A7
DI
DD
SS
CD DSP selection pins
Clock output pin
Sync signal input pin
Data input pin
Sync signal input pin
Power supply pin (+5 v)
Enable input pin
Data output pin
Data input pin
Clock input pin
Data input pin
Ground pin (GND)
Color bar selection pin
Graphic data discrimination output pin
DRAM control input pin
DRAM output pin
DRAM output pin
DRAM output pin
DRAM output pin
DRAM output pin
DRAM output pin
DRAM output pin
DRAM output pin
DRAM output pin
DRAM output pin
DRAM output pin
DRAM output pin
DRAM input/output pin
DRAM input/output pin
DRAM input/output pin
DRAM input/output pin
Blank signal output pin
Composite sync output pin
Pin Name
3ST
3ST
3ST
3ST
3ST
3ST
Out
Out
Out
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
In
In
In
In
In
In
In
In
In
In
Negative DRAM column address strobe signal output
Negative DRAM data write enable signal output
Negative DRAM data read enable signal output
Negative DRAM row address strobe signal output
LC7874E
Negative Composite sync signal output
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Polarity
—
—
—
Subcode R to W read clock output
Subcode frame sync signal input (MORE+ input)
Subcode R to W data input (MORE+ input)
Subcode block sync signal input (MORE+ input)
Digital power supply
Serial input/output data control input (MORE+ input)
Serial data output (Nch open-drain)
Serial data input (MORE+ input)
Serial data input/output clock input (MORE+ input)
Control signal input invalidating subcode data (MORE+ input)
GND
L: Normal mode, H: Color bar output (built-in pull-down resistor)
Goes high when graphics data is input (can be reset low by command
control).
Signal input setting DRAM connection pin to high impedance (MORE+
input)
DRAM address (A0) output
DRAM address (A1) output
DRAM address (A2) output
DRAM address (A3) output
DRAM address (A4) output
DRAM address (A5) output
DRAM address (A6) output
DRAM address (A7) output
DRAM data (D0) input/output
DRAM data (D1) input/output
DRAM data (D2) input/output
DRAM data (D3) input/output
Video signal blanking period output
S1
0
1
0
1
S2
0
0
1
1
LC7861N/67
LC7860K/63
Setting prohibited
LC7868/62X/63X
Selected CD DSP
Function
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