IDT5991A-2JI IDT [Integrated Device Technology], IDT5991A-2JI Datasheet - Page 2

• Manufacturer Part Number: IDT5991A-2JI
• Description: PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
• Manufacturer: IDT [Integrated Device Technology]

PIN CONFIGURATION
PIN DESCRIPTION
NOTE:
1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[
in effect unless nF[
PROGRAMMABLE SKEW
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit t
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF
IDT5991A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
GND/ sOE
Output skew with respect to the REF input is adjustable to compensate
Pin Name
V
TEST
nQ[
nF[
CCQ
GND
V
V
REF
FB
FS
CCN
CCQ
V
1:0
1:0
/PE
CCQ
(1)
]
]
V
GND
GND
/PE
4Q
4Q
CCN
(1)
3F
4F
4F
1
0
1
1
0
1:0
] = LL.
PWR
PWR
PWR
Type
5
6
7
8
9
10
11
12
13
OUT
I N
I N
I N
I N
I N
I N
I N
14
4
15
3
TOP VIEW
16
2
PLCC
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control
Summary Table) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q
the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[
controls for individual banks when nF[
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.)
Four banks of two outputs with programmable skew
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
17
1
32
18
31
19
30
20
1:0
29
28
27
26
25
24
23
22
21
control pins. In order
U
2F
GND/sOE
1F
1F
1Q
1Q
GND
GND
V
which is of the
CCN
0
1
0
0
1
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain
1:0
] = LL. Set GND/sOE LOW for normal operation.
2
ABSOLUTE MAXIMUM RATINGS
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
CAPACITANCE
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF
Parameter
Symbol
V
T
T
J
STG
I
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
C
IN
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Supply Voltage to Ground
DC Input Voltage
Junction Temperature
Storage Temperature
Description
Input Capacitance
Description
0
and 3Q
1:0
(T
control pins.
A
1
= +25°C, f = 1MHz, V
) in a LOW state - 3Q
1:0
0
] pins act as output disable
Typ.
and 3Q
5
–65 to +150
IN
–0.5 to +7
–0.5 to +7
= 0V)
Max
150
1
Max.
may be used as
7
(1)
Unit
Unit
°C
°C
pF
V
V