A43L8316AV AMICC [AMIC Technology], A43L8316AV Datasheet - Page 27

• Manufacturer Part Number: A43L8316AV
• Description: 128K X 16 Bit X 2 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

(September, 2003, Version 1.0)
Page Read & Write Cycle at Same Bank @Burst Length=4
CLOCK
ADDR
A8/AP
(CL=3)
CKE
RAS
CAS
(CL=2)
DQM
CS
DQ
DQ
WE
BA
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
0
Row Active
(A-Bank)
Ra
Ra
2. Row precharge will interrupt writing. Last data input, t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
1
command to avoid bus contention.
before end of burst. Input data after Row precharge cycle will be masked internally.
2
t
RCD
3
(A-Bank)
Ca0
Read
4
5
(A-Bank)
Read
Cb0
Qa0
6
Qa1
Qa0
7
Qb0
Qa1
*Note 2
8
*Note1
Qb0
Qb1
9
26
High
RDL
10
(A-Bank)
before Row precharge, will be written.
Write
Dc0
Dc0
Cc0
11
Dc1
Dc1
12
t
CDL
(A-Bank)
Dd0
Dd0
Write
Cd0
13
Dd1
Dd1
14
AMIC Technology, Corp.
*Note3
t
*Note 2
RDL
15
Precharge
(A-Bank)
16
A43L8316A
17
: Don't care
18
19