HFA3783IN96 INTERSIL [Intersil Corporation], HFA3783IN96 Datasheet - Page 19

• Manufacturer Part Number: HFA3783IN96
• Description: I/Q Modulator/Demodulator and Synthesizer
• Manufacturer: INTERSIL [Intersil Corporation]

The four registers are as follows:
R Counter: Division factor “R” in binary weight format with
R(0) as 2
the stable reference signal.
A/B Counter: A combination of binary weighted integer
division factors for the “N” counter as explained by the
relationship P*B+A.
Operational Mode: These register bits control the Charge
Pump operation, Prescaler “P” setting, the power down
feature of the PLL and the functions of the LD output pin.
Offset Calibration: These register bits control the division
ratio, in binary weight, for the SAR clock and a special
baseband output state for the Low Pass Filter.
NOTE: At power up (V
the Operational Mode register before any sequence of the
remaining registers.
Operational Modes Description
Bit M(0): This bit is normally set at one for the PLL
operation. Setting to zero can save up to 6mA of supply
current by disabling the PLL, although the serial interface is
always active for loading data. This operational mode bit
controls the serial interface at power up and it is important to
be loaded first, after application of V
Bit M(2): Selects the prescaler “P” for either 16 or 32.
Bits M(3),M(4): These bits select the desired Charge Pump
current from 250 A to 1mA in four steps.
Bits M(5), M(6): Programming 00 will set the Charge Pump
to “source” current when the VCO frequency is below the
desired frequency. It is used for VCO’s where the frequency
increases with increase in the voltage control. Programming
01 sets the Charge Pump to sink current when the VCO
frequency is below the desired frequency. It is used for
VCO’s where the frequency increases with decrease in the
voltage control (Negative KVCO).
Bits M(8), M(7) and M(13): These bits define the LD output
multiple operation. During the lock detect operation, the LD
output follows the phase comparator output and can be used
with external integration, as a frequency lock monitor
function. LD output can be shorted to ground or used as a
monitor pin for either the output of the “R” counter divider or
the [P*B+A] dual modulus divider. In addition, it can be used
as the serial register read back for testing purposes in a
FIFO mode (not the latched register/counters themselves)
by reading the MSB on the falling edge of LE and the
remaining bits on the rising CLK edges.
Bits M(14), M(15): These bits set the Charge Pump
operation for normal operation, constant sink or source and
in a high impedance state. The high impedance state allows
for external control.
0
and so on, for a decimal integer division ratio for
CC
application), it is important to load
19
CC
.
HFA3783
DC Offset Calibration Counter Description
Bits C(0) to C(6): Set a binary weighted decimal integer
number for the stable reference input frequency division
ratio. The ratio is used by the SAR for DC Offset Calibration
in the HFA3783 and previously described in the Low Pass
Filters section of this document.
Bit C(11): Enables a DC hold circuit which allows AC
coupling of the baseband signals to a processor A/D’s. A
common mode voltage applied to the baseband outputs
during transmit mode switching reduces the coupling
capacitors charging times.
Quadrature Modulator
The differential baseband signals for the HFA3783
modulator require a controlled common mode voltage for
proper operation of the device. Carrier suppression is
consequently a function of the common mode DC match
between the differential legs of each of the “I” and “Q”
channels. The modulator bandwidth is very wide and need to
be limited by external means. The inputs are equivalent to
driving the up conversion quadrature mixers directly;
therefore provisions for shaping the baseband signals before
up conversion have to be made externally. Shaping can be
accomplished either by an external filter or by pre-shaping in
a baseband processor. Baseband signals up to 500mVpp
differential can be used at the “I” and “Q” ports.
Centered upon a common mode voltage, the 500mVpp pre-
shaped differential signals were used for the compression
characteristics specified in this document. By reducing the
magnitude of these signals improved low distortion
modulation characteristics can be realized. The quiescent
current for the upconversion mixers is established by the
common mode input DC signal. By setting the common
mode voltage to zero during the receive mode, power
dissipation and mixer noise in the transmit path is reduced.
The common mode voltage, routed through the baseband
processor for temperature and V
established by the HFA3783’s on board 1.2V reference. This
reference is inactive during the power down mode.
The quadrature up converter mixers are also of a doubly
balanced design. “I” and “Q” up converter signals are
summed and buffered to drive the next stage, the AGC
amplifier. As with the demodulators, both modulator mixers
are driven from the same quadrature LO generator. These
mixers feature a phase balance of 2
balance of 0.5dB from 70 to 600MHz. These qualities are
reflected into the SSB characteristics. For differential “I” and
“Q”, 100KHz sinusoidal inputs of 375mVpp, 90
carrier feedthrough is typical -43dBc with typical sideband
suppression of 43dBc at 374MHz.
A differential open collector linear output AGC amplifier with
70dB of dynamic range follows the mixers. This amplifier is
based in a tight controlled voltage and temperature current
CC
tracking, is normally
o
and amplitude
o
apart, the