HFA3783IN96 INTERSIL [Intersil Corporation], HFA3783IN96 Datasheet - Page 15

• Manufacturer Part Number: HFA3783IN96
• Description: I/Q Modulator/Demodulator and Synthesizer
• Manufacturer: INTERSIL [Intersil Corporation]

and IF mixers out of compression. An external resistor and
capacitor set both the desired threshold voltage and time
constant. Figures 29 and 30 illustrate the typical current
output of the Peak Detector for input voltage levels between
100 and 200mVpp.
Quadrature Demodulator
The output of the AGC amplifier is AC coupled to two doubly
balanced quadrature differential mixers, for “I” and “Q”
demodulation. With full balanced differential architecture,
these mixers are driven by an accurate internal Local
Oscillator (LO) chain as described later. The voltage gain for
both mixers is well matched with a typical value of 8V/V.
Low Pass Filter and DC Offset Correction
To cover baseband signals from DC to 7.7MHz, the outputs
of the baseband down converter mixers are DC coupled to
the Low Pass Filter stages. For true DC response, the
combination of all DC offsets (mixer, LPF and buffers) needs
to be calibrated for accurate baseband processing. This
calibration can be performed at any time during the receive,
transmit or power down modes. Figure 2 depicts the
baseband low pass receive filter implementation and Figure
3 shows the calibration internal timing diagram of the
HFA3783. Referring to channel “I” for example, calibration
begins with the auto balanced comparator measuring the
differential offset between the RXI+ and RXI- outputs. The
comparator’s output is fed to a decision circuit which
changes the condition of a Successive Approximation
Register (SAR) state control. The SAR controls 8 bits of a
current output Digital to Analog Converter (IDAC) which is
divided by weight into a LPF section (2 pole) and a buffer
amplifier. The currents are searched and set to bring the
offset to a minimum. The LPF has a fixed gain of 2.5V/V and
the buffer adds a 1.25V/V final gain to the receive chain.
Referring to Figure 2, clocking to the SAR is provided by a
programmable division of the REF_IN signal. (Used for the
PLL as the stable reference.) The frequency of the reference
signal is divided down by the register setting of the offset
calibration counter. (Details for setting this counter can be
found in the Programming the PLL Synthesizer and DC
Offset Clock section.)
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HFA3783
The output of the calibration counter is again divided by 2
and the period used to generate the time slots of a state
sequence. The calibration cycle is initialized by a rising edge
on the HFA3783 CAL_EN pin. The state sequence slots 1 to
7 are used to settle all circuits in case the device is in the
power down mode, slots 8 to 10 are used to calibrate the
offset comparators (auto balancing) and slots 13 to 21
perform the search with an initial value of approximately + or
- 400mV differential DC level. The comparator reads the
direction and level of the offset and sets the next level and
polarity at + or -400/2 mV. The process continues until slot
21 in a divide by 2 polarity and minimum offset search. The
contents of the SAR are kept in slot 22 which holds the IDAC
in storage mode until a new positive edge is provided to the
CAL_EN pin. In receive mode, the AGC amplifiers are turned
off during the calibration cycle. A typical calibration time from
10 to 25 S is suggested for optimum accuracy.
The baseband outputs of the LPF buffer amplifier drive
differential loads of 5K with a common mode voltage of
typically 1.17V.
An extra feature of the LPF allows for AC coupling of the
baseband differential outputs. To avoid discharging of the AC
coupling capacitors between transmit and receive states a
common mode voltage can be applied to all outputs. An
onboard programmable bit control establishes the
application with 4 internal resistors and switches.
LO Quadrature Generator
The In Phase and Quadrature Local oscillator signals are
generated by a divide by two circuit that drives both the up
and down conversion mixers. With a fully balanced
approach, the phase relationship between the two
quadrature signals is within 90
frequency range. The input signal frequency at the LO_IN
pin needs to be twice the desired Local Oscillator frequency.
The high impedance differential LO_IN+ and LO_IN- inputs,
which are driven by an external VCO, can be used single
ended by capacitively bypassing one input to ground. The
user needs to terminate the VCO transmission line into the
desired impedance and AC couple the active LO_IN input.
Divide by two LO generation often requires rigid control of
signal purity or duty cycles. The HFA3783 has an internal
duty cycle compensation circuit which eases the
requirements of rigidly controlled duty cycles. Second
harmonic contents up to 10% are acceptable.
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for a wide 70 to 600MHz