sdn0080g Avant Electronics Corporation, sdn0080g Datasheet - Page 5

• Manufacturer Part Number: sdn0080g
• Description: 80-segment Dot-matrix Stn Lcd Driver
• Manufacturer: Avant Electronics Corporation

3.2
Table 2 Pin signal description.
To avoid a latch-up effect at power-on: V
Pin
number
1~80
81
82, 83,
84
85
86
87
88
89
90
91
92, 93,
94
95, 96,
97, 98
99
100
2005 Oct 03
Avant Electronics
Signal description
O1~O80
CDI
V1, V3, V4
V
M
LOAD
V
DISPOFF
V
R/L
NC
DI4 ~ DI1
CP
CDO
EE
SS
DD
SYMBOL
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output Cascading output when the SDN0080G are used in cascade.
I/O
Segment driver output.
Please refer to Table 3 for output voltage level.
Chip Disable pin.
When CDI=High, on-chip data reception circuit is disabled and data can not be
sent into the SDN0080G.
When CDI=LOW, data can be sent into the SDN0080G.
LCD bias voltage.
V1 and V
V3 and V4 are unselected levels.
Negative power supply for LCD bias.
Frame signal.
Display data (80 bits) latch clock. At the falling edge of the LOAD signal, 80-bit
segment data is transferred from the first latch to the second latch for output. (
Refer to Fig. 1, Functional Block Diagram.
Ground.
Display Disable.
When DISPOFF=L, the outputs O1~O81 are all at a fixed level of V1.
Power supply for control logic.
Shift direction control for display data reception from a controller.
No Connection.
These pins are not used in application and must be left open.
4-bit parallel data bus for interfacing with a controller.
The 4 bits of data are latched into the SDN0080G at the falling edge of the CP
clock.
Please refer to Fig 3.
Display data latch clock.
4 bits of display data (DI1~DI4) are latched into the internal 80-bit latch at the
falling edge of CP.
Please refer to Fig 3.
SS
− 0.5 V < voltage at any pin at any time < V
EE
are selected levels.
80-Segment Dot-matrix STN LCD Driver
5 of 18
DESCRIPTION
DD
+ 0.5 V .
SDN0080G
data sheet (v3)