sdn0080g Avant Electronics Corporation, sdn0080g Datasheet

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sdn0080g

Manufacturer Part Number
sdn0080g
Description
80-segment Dot-matrix Stn Lcd Driver
Manufacturer
Avant Electronics Corporation
Datasheet
data sheet (v3)
To improve design and/or performance,
Avant Electronics may make changes to its
products. Please contact Avant Electronics
for the latest versions of its products
SDN0080G
80-Segment Dot-matrix
STN LCD Driver
DATA SHEET
2005 Oct 03

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sdn0080g Summary of contents

Page 1

... To improve design and/or performance, Avant Electronics may make changes to its products. Please contact Avant Electronics for the latest versions of its products data sheet (v3) DATA SHEET SDN0080G 80-Segment Dot-matrix STN LCD Driver 2005 Oct 03 ...

Page 2

... Avant Electronics 1 GENERAL 1.1 Description The SDN0080G is an 80-segment dot-matrix STN LCD driver paired with the SDN8000G 80-common driver. 1.2 Features • 80-output segment driver for dot-matrix STN LCD. • Display duty : 1/64 to 1/256 • Power-down mode (Display OFF) for reducing power consumption. ...

Page 3

... Level shifter (80 bits) 80 2nd Latch (80 bits) 80 1st Latch (80 bits) 4 Address Decoder Address Decoder 4 bits Data Bus Interface Address Counter Chip Disable & Shift Control Latch Control SDN0080G O79 O80 VDD VSS DISPOFF bits) CDO Fig.1 Functional Block Diagram data sheet (v3) ...

Page 4

... Oct 03 80-Segment Dot-matrix STN LCD Driver SDN0080G Fig.2 Pin diagram of QFP100 / LQFP100 package SDN0080G ...

Page 5

... Shift direction control for display data reception from a controller. No Connection. These pins are not used in application and must be left open. 4-bit parallel data bus for interfacing with a controller. The 4 bits of data are latched into the SDN0080G at the falling edge of the CP clock. Please refer to Fig 3. Display data latch clock. ...

Page 6

... In the above table, X= don’t care and must be tied either 4.2 Display Data Inputs (DI1~DI4) The SDN0080G has a 4-bit parallel data bus (DI1~DI4) to interface with a controller. A logic High of a bit represents an ON cell (black pixel on the LCD screen). Table 4 Data bits ...

Page 7

... T Storage temperature range stg Note: ≥ V1 > V3 > V4>V 1. The condition V DD 2005 Oct 03 80-Segment Dot-matrix STN LCD Driver unless otherwise specified PARAMETER input DD must always be met SDN0080G = 25±2°C. amb MIN. MAX. UNIT −0 °C ...

Page 8

... For the driver circuits (O1~O80), please refer to Section 11 Pin = |=0.5 V, where For the driver circuits (O1~O80), please refer to Section 11 Pin SDN0080G = 25±2 °C. amb MIN. TYP. MAX. 2.7 5.0 5 0. ...

Page 9

... DI1~DI4 data to the falling edge of the CP clock. Falling edge of the CP clock to DI1~DI4 data change. Note 1. Note 1. the CDO pin, Load=15pF and LOAD must comply with the following two conditions SDN0080G 0. 0.2V DD Fig.4 AC characteristics = 25 ±2 °C. amb MIN. ...

Page 10

... IC number 1 data acquisition period CDO(No.2) CDO(No.3) CDO(No.n) O1~O80 2005 Oct 03 80-Segment Dot-matrix STN LCD Driver one scan line ( pixels ) number 2 data acquisition period IC number 3 data acquisition period SDN0080G IC number n data acquisition period Fig.5 Output timing diagram data sheet (v3) ...

Page 11

... VDD (V1 (V3) O1 ~O80 Vc (V4 2005 Oct 03 80-Segment Dot-matrix STN LCD Driver 1 2 240 1 2 240 1 2 240 SDN0080G 240 1 2 Fig.6 1/240 duty timing chart VDD LCD 12R ...

Page 12

... Dot-matrix STN LCD Driver SDN0080G Vb V LCD 12R SDN0080G (1/16 LCD (2/16 LCD (14/16 LCD (15/16 LCD (16/16 LCD Fig.8 LCD bias voltage data sheet (v3) ...

Page 13

... APPLICATION CIRCUIT (240 X 640 DOT) In this application, 3 pcs of the SDN8000G and 8 pcs of the SDN0080G are used. Controller FLM DISPOFF LOAD M CP DI1~DI4 GND VDD DC/DC 1/16 Bias (LA5317M) Vref V EE COM1 DISP OFF COM2 COM3 VEE CP M COM238 DISPOFF COM239 ...

Page 14

... V4 EE inputs V EE 2005 Oct 03 80-Segment Dot-matrix STN LCD Driver CIRCUIT VDD VDD VSS VSS VDD VDD VSS VSS VDD EN1 VDD VEE EN2 VDD VEE VEE EN3 VDD VEE EN4 VDD VEE SDN0080G NOTES data sheet (v3) ...

Page 15

... When powering down the system, control logic must be shut off later than or at the same time with the LCD bias ( VDD 0V 0~50 ms Signal 0 second (minimum 2005 Oct 03 80-Segment Dot-matrix STN LCD Driver 1 second (minimum) 0 second (minimum) -30V Fig.10 Recommended power up/down sequence SDN0080G 1 second (minimum) 0~50 ms data sheet (v3) ...

Page 16

... PACKAGE INFORMATION SDN0080G QFP100 Package Outline Drawing ...

Page 17

... V) applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 °C. 2005 Oct 03 80-Segment Dot-matrix STN LCD Driver SDN0080G data sheet (v3) ...

Page 18

... Avant customers using or selling these products for use in such applications their own risk and agree to fully indemnify Avant for any damages resulting from such improper use or sale. 2005 Oct 03 18 data sheet (v3) SDN0080G ...

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