lc89058w Sanyo Semiconductor Corporation, lc89058w Datasheet
lc89058w
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lc89058w Summary of contents
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... IEC60958/61937 and JEITA CPR-1205. It supports demodulation sampling frequencies 192kHz. The LC89058W-E can easily replace the existing LC89057W-VF4A-E. The LC89058W-E incorporates a number of features for its low cost and is optimal for receiving digital data for AV amplifiers and receivers. ...
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... Continued from preceding page. • Equipped with a serial data input pin. Possible to switch with demodulation output automatically according to the state of the PLL circuit. • The fs reception range of S/PDIF interface can be limited. LC89058W-E can be set to a no-signal input state if the reception range is exceeded. • Supports data output that facilitates interfacing with DSP ...
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... S system bit clock output pin (16fs, 32fs, 64fs, 128fs) 23 SLRCK O S system LR clock output pin (fs/4, fs/2, fs, 2fs) 24 SDIN I External serial audio data input pin 5 LC89058W LC89058W Top view Table 5 ...
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... Pin 34 serves as the input pin for designating as the master or slave when pin 41 is held at the low level. * Pin 35 serves as the input pin for configuring the I/O of pins when pin 41 is held at the low level. * The DV DD and AV DD pins must be held at the same level and turned on and off at the same timing to preclude Latch-up conditions. LC89058W-E Function No.A1056-4/64 ...
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... RX5 9 RX6 10 LPF 13 XIN 29 Oscillation XOUT 28 Amplifier XMCK 27 LC89058W-E INT 35 Microcontroller I/F Cbit, Pc Demodulation & Lock detect PLL Clock Selector 34 CKST Figure 6.1 LC89058W-E Block Diagram AUDIO 33 XMODE RERR 36 SDIN 24 Data Selector RDATA 21 RMCK 16 RBCK 17 Clock RLRCK 20 Divider SBCK ...
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... Yes Input fs computed output 16kHz to 192kHz Microcontroller interrupt signal Yes (Low pulse, Low level output) 7.3 Added or Modified Functions Table 7.3: Differences between LC89057W-VF4A-E and LC89058W-E (Added or Modified Functions) Item Oscillation amplifier initial setting Suspended while PLL is locked PLL clock output 256fs or 512fs ...
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... Except MOSEL, PRSEL [1:0], OFDSEL, GPIO, SELMTD and RCKSEL, the command address of any inadvertently specified commands that are removed from the LC89057W-VF4A-E is assumed to be “0” and ignored. The new commands added to the LC89058W-E are allocated to command addresses 12, 13, and 14. LC89058W-E ...
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... IEC1937 DO18 DTS51 DO19 DTSES DO20 F0512 DO21 F1024 DO22 F2048 DO23 F4096 • The CCB addresses 0xEC and 0xED remain the same for both the LC89057W-VF4A-E and LC89058W-E. LC89058W-E LC89057W-VF4A-E 0xEB PO0 PO1 PO2 PO3 FSC0 FSC1 FSC2 FSC3 FSDAT0 ...
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... Figure 7.1 Change from LC89057W-VF4A-E to LC89058W-E (when the INT pin is set to pull-down) • In this case, the system that doesn't use a modulation function or a general-purpose I/O function can be replaced with LC89058W-E. • After the replacement, LC89058W-E is used on condition that it pins connect with GND and pin 48 open. LC89058W-E Pin.46 Pin ...
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... JP Open when LC89058W-E use Figure 7.2 Change from LC89057W-VF4A-E to LC89058W-E (when the INT pin is set to pull-up) 1 • After the replacement, pins can be used as general purpose I/O output function. (pin 48 open) • necessary to review the circuit pattern of the printed circuit board because the I/O setting of pin 48 differs from each other. 7.5.1.2.2 In case of “ ...
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... JP Short when LC89057W-VF4A-E use Figure 7.5 Change from LC89058W-E to LC89057W-VF4A-E (when the INT pin is set to pull-up) • After the replacement, pins can be used as general purpose I/O output function. However necessary to review the circuit pattern of printed circuit board because pin 48 has to GND. ...
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... Supply voltage Input voltage range Input voltage range Operating temperature Topr 8-2-1: RX1, RBCK, RLRCK, XIN, GPIO0, GPIO1, GPIO2, GPIO3 pins 8-2-2: RX0, RX2, RX3, RX4, RX5, RX6, SDIN, DI, CE, CL, XMODE pins LC89058W-E Symbol Conditions 8-1-1 8-1-2 8-1-3 8-1-4 8-1-5 8-1-6 Symbol Conditions ...
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... GPIO0, GPIO1, GPIO2, GPIO3, RXOUT2 output pins 8-3- −2mA 2mA: Output pins other than those listed above 8-3-7: Before capacitance of RX1 input pin, and reception frequency is possible up to 96kHz. 8-3-8: Ta=25°C, fs=96kHz 8-3-9: RX0, RX2, RX3, RX4, RX5, RX6 input pins LC89058W-E Symbol Conditions 8-3-1 8-3-2 ...
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... A frequency compatible with the XINSEL setting must be applied to XIN. 8-4-2: When RMCK and SBCK source clocks are identical 8-4-3: When SBCK is the PLL source clock RX0-6 (I) RMCK (O) (RMCKP=0) RBCK (O) RLRCK (O) RDATA (O) Figure 8.1 AC Characteristics of Demodulation function LC89058W-E Conditions 8-4-1 8-4-2 8-4-3 t WDI t WDI F MCK t BDO Ratings Unit ...
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... CE, DO delay time 8-5-1: CL has to lower before when CL is normal H clock. 8-5-2: Only when data write with CL of normal H clock. CL (I) CE (I) DI (I) DO (I) Figure 8.2 CCB Microcontroller Interface AC Characteristics LC89058W-E Conditions 8-5-1 8-5-2 t CLdw t CLuw t CEhold t DIhold t DIsetup t CLtoDO t CEtoDO ...
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... Table 9.2: Output Pin State When XMODE is Reset (XMODE=L) No. Pin name 1 RXOUT1 16 RMCK 17 RBCK 20 RLRCK 21 RDATA 22 SBCK 23 SLRCK 27 XMCK LC89058W-E Table 9.1: Pin Names and Settings Setting Normal system operation range Setting completed 3. > 200μs Setting input state Output state Pin State No. RXO output 32 XIN output 33 Low output 34 ...
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... Command writing is enabled by making the chip address settings with MOUT and addresses sent from the microcontroller. • The chip address setting is required even when only one LC89058W-E is used in the system. If the chip address is not set, the chip address is undefined and the microcontroller cannot control the system. When the microcontroller is not used, a chip address-setting pin is input open while XMODE is " ...
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... A master/slave function that allows multi-channel synchronized transfer using multiple LC89058W-Es is included. For this setting, connects either a 10kΩ pull-down or a pull-up resistor to CKST. • Set to the master mode normally, when single LC89058W used. When multiple LC89058W-Es are used, set one of them to the master mode and the others to the slave mode. ...
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... Oscillation amplifiers (XIN, XOUT, XMCK) • The LC89058W-E features a built-in oscillation amplifier. Connecting a quartz resonator, feedback resistor, and load capacitance to XIN and XOUT can configure an oscillation circuit. When connecting a quartz resonator, use one with a fundamental wave. Be aware that the load capacitance depends on the quartz resonator characteristics. ...
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... Consequently the input fs calculation restarts. At this time, the previous fs calculation value is reset and compared with the newly calculated fs value. Then those two values are found not identical, that’s why the error is temporarily issued. LC89058W-E R System Clock Source S System Clock Source ...
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... S/PDIF PLL Auto 1/N 512fs (N=1,2,4) (N=1,2,4) “PRSEL[1:0]” XOUT “XINSEL” XIN 12.288M 24.567M “AMPOPR[1:0]” GPIO0 LC89058W-E Lock/Unlock “PLLACC” 1/N “OCKSEL” “XRSEL[1:0]” 1/N (N=1,2,4) “EMCKP” “XMSEL[1:0]” 1/N (N=1, 2) Figure 10.2 Master Clock Block Diagram “RMCKP” RMCK “EXTSEL” ...
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... If 128kHz, 176.4kHz or 192kHz input is received when the PLLACC is set to 0 and the PRSEL [1:0] to 01, the DC characteristics of output directly sent to the RMCK pin cannot be guaranteed. In such a case, set the frequency to one half or quarter of the PLL clock frequency (PRSEL [1:0]=00 or 10). LC89058W-E *: When the data is judged to exceed the value of FSLIM [1:0] which limits the reception frequency of ...
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... Output clocks (RMCK, RBCK, RLRCK, SBCK, SLRCK) • The LC89058W-E features two clock systems (R and S systems) in order to supply the various needed clocks to peripheral devices such as A/D converter and DSP. • The clock output settings for the R and S systems are done with PLLACC, PLLDV1, PLLVD2, PRSEL[1:0], XRSEL[1:0], XRBCK[1:0], XRLRCK[1:0], PSBCK[1:0], PSLRCK[1:0], XSBCK[1:0], and XSLRCK[1:0]. • ...
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... Mute X’tal Source 12.288MHz “XINSEL” 12.288MHz 24.576MHz 24.576MHz “PSBCK[1:0]” 128fs 64fs 32fs 16fs “PSLRCK[1:0]” 2fs fs fs/2 fs/4 LC89058W-E Input fs Lock / Unlock Auto “PLLACC” PLL “PRSEL[1:0]” “XRSEL[1:0]” 1/1 1/2 1/4 XIN Mute “XMSEL[1:0]” 1/1 1/2 Mute PLL 64fs “XRBCK[1:0]” ...
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... RX0 to RX6 Digital data PLL status XIN clock PLL clock CKST (CKSTP=0) RERR RMCK **: When set to PTOXW[1:0]=00 (max.) LC89058W-E Digital data UNLOCK After PLL lock XIN clock (a): Lock-in stage LOCK Same timing as RERR PLL clock (b): Unlock stage Figure 10.5 Clock Switch Timing ...
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... LOCK PLL status RERR RMCK PLL clock RBCK RLRCK (c) When set to FSLIM[1:0]=10 (Receive frequency is limited to 48kHz or lower) Figure 10.6 Output Clocks Generated When Input Data Reception Is Limited LC89058W-E fs=192kHz LOCK PLL clock (a) When set to FSLIM[1:0]=00 (No limit on inputs) fs=192kHz LOCK XIN clock fs=192kHz ...
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... IEC60958 compatible S/PDIF data. The frequency of the clock supplied to XIN when RXMON is set is limited to 24.576MHz. LC89058W-E does not run at any clock frequency other than 24.576MHz. Moreover, since this function uses the XIN clock, the oscillation amplifier must be set in the continuous operation mode when RXMON is set. • ...
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... RX0, RX2, RX3, RX4, RX5, and RX6 are TTL input level compatible S/PDIF input pins with 5V-tolerance voltage. Coaxial Optical LC89058W-E LC89058W-E RX0 RX1 RX2 ≥470kΩ RX3 RX4 Optical etc. RX5 RX6 (a) Coaxial input circuit LC89058W-E RX0 RX1 RX2 RX3 RX4 Optical etc. RX5 RX6 (b) Optical input circuit Figure 10.7 S/PDIF Input Circuits No.A1056-28/64 ...
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... The initial value of output format is I • Output data is output synchronized with the RLRCK edge immediately after the RERR output becomes "L". RLRCK (O) RBCK (O) RDATA (O) MSB RLRCK (O) RBCK (O) RDATA (O) MSB 24bit LC89058W L-ch LSB MSB 24bit 2 (0 data output L-ch LSB ...
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... Serial audio data input format (SDIN) • LC89058W-E is provided with a serial data input pin of SDIN. • The format of the serial audio data input to SDIN and the demodulation data output format must be identical. • The initial value of modulation data output format is I • The SDIN data to be input must be in synchronization with the RBCK and RLRCK clocks. ...
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... PLL status. PLL status UNLOCK CKST CKSTP=0 RERR RDATA SDIN data PLL status LOCK CKST CKSTP=0 RERR RDATA Demodulation data Figure 10.10 Timing Chart of RDATA Output Data Switching LC89058W-E LOCK Muted (a): Lock-in stage UNLOCK Muted (b): Unlock stage Demodulation data SDIN data No.A1056-31/64 ...
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... MOUT pin is limited. The FSSEL[1:0] sets the contents of the MOUT pin output. FSSEL1 FSSEL0 LC89058W-E “ROSEL[2:0]” S/PDIF “RXSEL[2:0]” S/PDIF “RISEL[2:0]” “RDTSEL” “RDTSTA” DIR Figure 10.11 Data System Diagram Table 10.5: MOUT Pin Output Mode Settings MOUT Pin H Output Conditions When calculating 32kHz, 44 ...
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... If a setting which regard non-PCM data input as an error is made with RESEL, RERR turns to “H” when non-PCM data input is detected. At this time, the PLL locked status and various output clocks are subject to the input data, but the output data is muted. LC89058W-E No.A1056-33/64 ...
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... Input parity error (c): If occurs 8 or fewer times in succession, in case of non-PCM burst data 1occurrence Input data L-1 R-1 L-2 RERR RLRCK RDATA L-0 R-0 Figure 10.12 Example of Data Processing upon Parity Error Occurrence LC89058W-E Input Parity Error (a) “L” “L” “L” Output “L” “L” R-2 L-3 R-3 L-4 ...
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... Non-PCM signal. This information is used to read out the output register and identify the details of the non-PCM signal • The detection flags are cleared when fs is changed or when a PLL lock error or data error occurs. LC89058W-E OK 3ms to 144ms ...
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... The contents of the register are updated if INT turns to “L” before P0[3:0] is readout. 11.3.1.2 GPIO=0 (not using INT ) (1) The data inputs to the GPIO0, GPIO1, GPIO2, and GPIO3 pins are taken in when the CCB address 0xEB is set. (2) The data read from the PO[3:0] is transferred to the microcontroller. At the same time, the data in the register is cleared. LC89058W-E No.A1056-36/64 ...
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... The data input to GPIO3 can be muted by EDTMUT. • EMCKP and EDTMUT are enabled when GPIOS=1 is set. • The above settings are valid only when the master mode is set and must not be set when the slave mode is set. LC89058W-E Lock judgment 4 ...
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... Clearing INT at the same time of readout of an output register is carried out immediately after the output register ______ 0xEA is set. However, INT is not cleared other than the 0xEA setting. LC89058W-E _____ INT , CL, CE, DI, DO) ______ INT outputs OR calculation result of the selected Table 12 ...
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... CE. • outputs are shared using multiple LC89058W-E units possible to set the DO outputs of the LC89058W-E units of which data is not to be read to be always in the high impedance state with DOEN. With this setting, only the targeted outputs can be read. ...
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... Hi-Z Figure 12.4 Output Timing Chart (Normal H clock) (CL is lowered before CE is raised, and DO0 need be read with port) LC89058W-E A3 CAL CAU DI2 DI3 DI4 DI5 DI6 A2 A3 CAL CAU DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 (CL need not be lowered before CE is raised ...
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... TEST Addr: Command address • The shaded parts of DI8 to DI15 in the command area are reserved bits. Input must be doing "0". • Command addresses 11 and 15 are reserved for testing purposes. Writing to these addresses is prohibited. LC89058W-E Table 12.3 Write Register Map DI14 DI13 ...
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... Setting of sampling frequency reception range for input digital signal 00: No limit (initial value) 01: fs≤96kHz (when exceeded, data is muted and clock is set to XIN system output) 10: fs≤48kHz (when exceeded, data is muted and clock is set to XIN system output) 11: Reserved LC89058W-E DI5 DI4 DI3 0 ...
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... Stop AMPOPR [1:0] Oscillation amplifier operation setting 00: Permanent continuous operation (initial value) 01: Reserved 10: Automatic stopping of oscillation amplifier while PLL is locked 11: Stop • In order to replace LC89057W-VF4A-E, setting contents of the AMPOPR[1:0] are different from those of LC89057W-VF4A-E. LC89058W-E DI5 DI4 DI3 DI13 DI12 DI11 ...
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... Don’t do the setting to which RMCK=3.072MHz is output by XRSEL [1:0]=10(1/4 output) setting when XIN=12.288MHz is input because it doesn't satisfy the output setting condition of RBCK and SBCK. • Setting of XRBCK [1:0] relate to setting of RMCK output clock. RBCK output clock is set to become 1/2 or less of RMCK output clock at XIN source. LC89058W-E DI5 DI4 DI3 ...
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... XSLRCK [1:0] SLRCK output frequency setting during XIN source 00: 48kHz output (initial value) 01: 96kHz output 10: 192kHz output 11: Muted • Setting of XSBCK [1:0] relate to setting of RMCK output clock. SBCK output clock is set to become 1/2 or less of RMCK output clock at XIN source. LC89058W-E DI5 DI4 DI3 ...
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... If the oscillation amplifier is set to stop automatically when the PLL gets locked, XIN source switching from the PLL locked status disables the clock output. Be sure to set the oscillation amplifier to the continuous operation mode when switching the clock source to the XIN source. LC89058W-E DI5 DI4 ...
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... RX0 input data (initial value) 001: RX1 input data 010: RX2 input data 011: RX3 input data 100: RX4 input data 101: RX5 input data 110: RX6 input data 111: “L” fixed output LC89058W-E DI4 DI3 DI2 DI12 ...
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... Falling RDATA data change (initial value) 1: Rising RDATA data change SLRCKP SLRCK output polarity setting 0: "L" period: L-channel data; "H" period: R-channel data (initial value) 1: "L" period: R-channel data; "H" period: L-channel data LC89058W-E DI4 DI3 DI2 1 0 ...
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... The burst preamble Pc update flag also compares the 16 bits of data of the previous block with those of the current data. If they are identical, an update flag is output. • The 4-bit input data updated flag when the general-purpose I/O parallel input is set, is output only when a change has occurred in the sampling data with a clock of 24kHz. LC89058W-E ______ INT output contents setting DI5 ...
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... ERWT[1:0] defines the interval of time for RERR to output error cancellation ("L") after PLL is locked. Since demodulated audio data is output after RERR cancels an error, you need to change this setting if the situation that the head of data is missing is a problem. LC89058W-E DI5 DI4 ...
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... PI2 Contents of data output to the GPIO2 pin when the general-purpose I/O parallel output is set 0: L (initial value PI3 Contents of data output to the GPIO3 pin when the general-purpose I/O parallel output is set 0: L (initial value LC89058W-E DI4 DI3 DI2 DI12 DI11 ...
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... Set the PLL clock generated when 88.2kHz or 96kHz is received with PLLAC=1 0: 256fs output (initial value) 1: 512fs output RMCKP DIR block RMCK output setting 0: Normal output (initial value) 1: Inverted output CKSTP CKST output polarity setting 0: Normal high output (initial value) 1: Normal low output LC89058W-E DI4 DI3 DI2 DI12 DI11 DI10 RMCKP ...
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... RX5 input data 111: RX6 input data • GPIOS setting is needed when RMCK, RBCK, RLRCK, and RDATA output are changed with EXTSEL. • RMCK, RBCK, RLRCK, and RDATA output don’t change even if it sets to EXTSEL=1 in the state of GPIOS=0. LC89058W-E DI5 DI4 DI3 ...
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... MOUT output contents setting (output “L” when PLL unlock status or when a value other than those listed below is calculated) 00: Output “H” when 32kHz/44.1kHz/48kHz is calculated (Initial value) 01: Output “H” when 64kHz/88.2kHz/96kHz is calculated 10: Output “H” when 128kHz/176.4kHz/192kHz is calculated 11: Output “H”when 64kHz/88.2kHz/96kHz or higher is calculated LC89058W-E DI4 DI3 DI2 0 0 ...
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... OGPIO DO15 OEMPF DO16 CSBIT1 DO17 IEC1937 DO18 DTS51 DO19 DTSES DO20 DO21 DO22 DO23 DO24 DO25 DO26 … … DO45 DO46 DO47 LC89058W-E Table 12.4 Read Register Map 0xEB PO0 PO1 PO2 PO3 FSC0 FSC1 FSC2 0 FSC3 - - - CS bit10 - CS bit11 - CS bit12 - CS bit13 - ...
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... RX5 input detection 0: No input data in RX5 1: Input data exist in RX5 RXDET6 RX6 input detection 0: No input data in RX6 1: Input data exist in RX6 • For readout of RXDET[10:0], RXMON must be set to "1" beforehand. LC89058W-E DO5 DO4 DO3 RXDET4 RXDET3 DO2 DO1 ...
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... Channel status emphasis detection (output of status during readout pre-emphasis 1: 50/15μs pre-emphasis exists • Concerning OERROR and OUNPCM, the status of RERR and _______ regardless of the INToutput setting. LC89058W-E DO13 DO12 DO11 OUNPCM OCSRNW ____________ AUDIO that are subject to RESEL setting are read ...
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... Pa, Pb detected DTS51 DTS-CD/LD 5.1 channel sync signal detection 0: DTS-CD/LD sync signal not detected 1: DTS-CD/LD sync signal detected DTSES DTS ES-CD/LD 6.1 channel sync signal detection 0: DTS ES-CD/LD sync signal not detected 1: DTS ES-CD/LD sync signal detected LC89058W-E DO20 DO19 DO18 0 DTSES DTS51 DO17 DO16 IEC1937 CSBIT1 No ...
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... Input data fs calculation result "xxxx": See code table. Table 12.5 Code Table of Input fs Calculation Result (Ta = 25° 3.3 V) FSC3 FSC2 LC89058W-E DO5 DO4 DO3 FSC1 FSC0 PO3 FSC1 FSC0 ...
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... Bit 15 DO16 Bit 16 Source number DO17 Bit 17 DO18 Bit 18 DO19 Bit 19 DO20 Bit 20 Channel number DO21 Bit 21 DO22 Bit 22 DO23 Bit 23 LC89058W-E Contents Register DO24 DO25 DO26 DO27 DO28 DO29 DO30 DO31 DO32 DO33 DO34 DO35 DO36 DO37 DO38 DO39 DO40 ...
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... The burst preamble Pc data can be read with the demodulation function. • The 16 bit-data of burst preamble Pc are output with LSB first. • For readout, set the CCB address to OxED. • The relation between the read register and burst preamble Pc data is shown below. LC89058W-E Table 12.7 Burst Preamble Pc Read Registers Register Bit No. ...
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... DO6 DO7 0 1 DO12 to 8 DO15 LC89058W-E Table 12.8 Burst Preamble Pc Field Contents NULL data Dolby AC-3 data Reserved Pause MPEG-1, layer 1 data MPEG-1, layer 2, 3 data, or non-extended MPEG-2 Extended MPEG-2 data Reserved MPEG-2, layer 1, low sampling rate ...
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... C0 ∗∗ C1 ∗∗ R0 LC89058W-E 12.288MHz 24.576MHz LC89058W SQFP48 (9X9 Table 13.1 Application Example ...
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... SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2008. Specifications and information herein are subject to change without notice. LC89058W-E PS No.A1056-64/64 ...