lc89052t Sanyo Semiconductor Corporation, lc89052t Datasheet
lc89052t
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lc89052t Summary of contents
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... Ordering number : ENN7457 1. Overview The LC89052T is an audio LSI that demodulates according to the data format for the data transferred between digital audio devices via the IEC 60958/61937 and EIAJ CP-1201. It supports sampling frequencies 192kHz and output data lengths bits. ...
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... The TTL input ports can support 5V interface operation. Package: TSSOP-24 4. Pin Assignments XOUT ERROR E / INT AUDIO LC89052T 1 24 XIN 2 23 SDIN DATAO LRCK BCK CKOUT LC89052T DGND AGND LPF UGPI RXIN DV DD Top view No.7457-2/42 ...
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... S mode ; Low: right channel, High: left channel mode ; Low: left channel, High: right channel. 1) I/O voltage handling : pins : –0.3 to +3.6V pins : –0.3 to +5. prevent logic circuit latch-up, all power supply must be applied or removed simultaneously. LC89052T Table 5.1 Pin Functions Function * ** *** No.7457-3/42 ...
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... Block Diagram Microcontroller I/F E/INT 9 UGPI 11 Demodulation & Lock detection RXIN 12 LPF 15 PLL XIN 24 XOUT 1 LC89052T CE PD AUDIO calu. Data buffer Clock selector Amp & ERROR 19 CKOUT Audio 20 BCK I/F 21 LRCK 22 DATAO 23 SDIN No.7457-4/42 ...
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... PD, CE, CL, and DI pins 7.3 Input and Output Pin Capacitances Table 7.3 Input and Output Pin Capacitances Parameter Symbol Input pins C IN Output pins C OUT 7-3 25° 1MHz LC89052T Symbol Conditions 7-1-1 7-1-2 7-1-3 7-1-4 7-1-5 7-1-6 _____ UGPI, CKOUT, BCK, LRCK, and DATAO pins. ...
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... Operating mode: PLLSEL = "0", AMPOPR = "0" 44.1kHz 30pF 7-4-7 : Low power mode condition 1) : 7-4-8 : Low power mode condition 2) : PDOWN [1:0] = "01", XIN = 11.2896MHz 30pF 7-4-9 : Low power mode condition 3) : PDOWN [1:0] = "10", XIN = 11.2896MHz 30pF LC89052T Conditions min 7-4-1 0.7DV DD 7-4-2 – ...
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... CKT 7-5-1 : PLLCK [1:0] = "00" 7-5-2 : Settings other than PLLCK [1:0] = "00". 7-5-3 : XISEL [3:0] = "0000" 7-5-4 : XISEL [3:0] = "0001" 7-5-5 : XISEL [3:0] = "0010" 7-5-6 : XISEL [3:0] = "0100" 7-5-7 : XISEL [3:0] = "0101" 7-5-8 : XISEL [3:0] = "0110" 7-5-9 : When signal output is set during a transitional period of clock switching. UGPI CKOUT BCK DATAO LRCK LC89052T Conditions min 7-5-1 30 7-5-2 30 7-5-3 7-5-4 7-5-5 7-5-6 7-5-7 7-5-8 2 7-5-9 t CKT ...
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... delay time t CLtoDO delay time t CEtoDO 7-6-1 : INTOPF = "1", INTSEL = "1", and fs is the input sampling frequency. t INTud E/INT t CLuw DIsetup DI DO Hi-Z Figure 7.2 Microcontroller AC Characteristics LC89052T Symbol Conditions min 200 7-6-1 5 100 100 CLdw t CEsetup ...
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... When the oscillator amplifier is stopped by the AMPOPR in a low-power mode setup with PDOWN[1:0] or when this circuit is already stopped impossible for the LC89052T to provide a clock output. Thus the AMPOPR takes precedence. Note that the PLLOPR setting is invalid and the PLL circuit is stopped. ...
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... Mode (6) applies when the PLL circuit is locked. When the PLL circuit is unlocked, all circuits are stopped since no clock signal is supplied from XIN pin mode (7), the states immediatly before the setup is retained. LC89052T Table8.1 Low-power Modes PDOWN1 PDOWN0 × ...
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... Clocks 8.3.1 PLL (LPF) The LC89052T incorporates a VCO (Voltage Controlled Oscillator) that can synchronize with sampling frequencies of 30kHz to 195kHz. The locking frequency is selected with PLLCK[1:0]. The VCO circuit can be stopped with PLLOPR. The range of input data that can be received differs depending on the settings of PLLCK[1:0]. ...
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... However, continuity at clock switching time and correct input fs calculation are not guaranteed. The LC89052T supports a structure in which CKOUT pin is connected to the XIN pin to set XISEL3, requiring no oscillator. However, since only VCO can be used as the source clock, the VCO free-running frequency (10M to 16MHz) is output from the CKOUT pin when the PLL is not locked ...
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... If you use the following procedure to switch between 512fs and (512/2)fs, the BCK and LRCK output clock continuity can be maintained, and the CKOUT output clock frequency can be held within a narrow band. Other PLLCK[1:0] switching would result in a lock error. No CKOUT output Figure 8.4 Flowchart for CKOUT Output Clock Narrow Band Operation LC89052T 0 Unlocked XIN 512fs set PLLCK0=0 ...
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... If the audio output format is set to bi-phase data output, the BCK output clock frequency is doubled to 128fs when the PLL circuit is locked. However, when unlocked, a BCK signal shown in the above tables is output. Note that the clock continuity is not maintained when this output format is set. LC89052T XISEL0 CKOUT pin ...
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... CKOUT are output from BCK and LRCK pins. However, these clock frequencies vary depending on the LC89052T sample and fluctuate depending on supply voltage and operating environments. Therefore, the frequency is not fixed. You need to take care when using the CKOUT, BCK, and LRCK clocks while the PLL circuit is unlocked ...
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... The RXIN pin supports TTL levels. This allows a 5V-optical reception module to be connected directly. 8.4.2 Setting the bi-phase mark modulated input data reception range The LC89052T allows the user to set the upper limit sampling frequency of the receivable input data and can receive input data of specific sampling frequencies. ...
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... MSB first left-justified data output (OFSEL[2 : 0]=000) LRCK BCK MSB DATAO bits LRCK BCK DATAO (2) : MSB first right-justified data output (OFSEL[2 : 0]=010, 011 or 100) Figure 8.6 Data Output Timing (Normal Mode) LC89052T L-ch LSB MSB bits L-ch R-ch LSB MSB bits 2 ( ...
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... C P LSB LRCK BCK LSB -24 bit- DATAO LRCK BCK LSB -24 bit- DATAO (5) : NRZ data LSB first left-justified output (OFSEL[2 : 0]=111) Figure 8.7 Data Output Timing (Special Mode) LC89052T L-ch MSB LSB (3) : Biphase data output (OFSEL[2 : 0]=101) L-ch MSB LSB -24 bit- ...
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... LRCK BCK SDIN MSB bits LRCK BCK MSB SDIN bits LRCK BCK SDIN Figure 8.8 Example of Serial Audio Data Input Timing LC89052T L-ch LSB MSB LSB bits (0) : MSB first left-justified data input L-ch R-ch LSB MSB LSB bits 2 ( data input ...
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... These modes are switched by FS4XIN not possible to monitor the fs calculation result of 32k to 192kHz in the same mode system where the XIN and CKOUT pins are connected and no oscillator is required is being setup, the fs calculation result will always be "out of range". LC89052T LOCK UNLOCK Demodulated data ...
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... PCM data is recognized. 8.5.4 Other errors Even when ERROR has turned to low, the LC89052T always acquires bits (sampling frequency) of the channel status and compares the current data with the data of the previous block. If any differences are found, ERROR is immediately set to high and processes similar to those for the PLL lock error are carried out ...
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... The figure below presents an example of the data processing performed when a parity error occurs. An error occurs Input data L-1 R-1 L-2 R-2 L-3 R-3 L-4 R-4 ERROR LRCK L-0 R-0 L-1 DATAO Previous data value Figure 8.10 Data Processing Example for a Parity Error (When PCM data is received) LC89052T Input parity error (a) Input parity error (b) Low Previous data Low Low Previous data Low L-5 R-5 L-6 R-6 L-7 R-7 L-8 R-8 ...
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... Emphasis information output (E/INT) E/INT is shared by the microcontroller interface interrupt function. However, in the initial state, it outputs the presence or absence of emphasis with a time constant of 50/15 s for use in consumer products or broadcast studios. E/INT pin Low High LC89052T ______________ Table 8.10 AUDIO Output ...
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... The application must set GPIDAT to "0" to have the optical module supply data. That is, the controlled with GPIDAT, and the current drain can be minimized when the optical module is not used. LC89052T __________ Figure 8.12 UGPI Output Example (Power supply control signal for an optical module) LC89052T __________ UGPI ) __________ UGPI pin. __________ ...
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... Note that after a reset, the initial value of GPIDAT is set to "1", so high level is output from initial value of the switching signal is high level. LC89052T __________ UGPI Output Example (Signal that controls the switching of data input) Figure 8.13 LC89052T __________ UGPI output. UGPI SW RXIN __________ UGPI ...
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... Digital data PLL lock state Locked XTAL clock VCO clock UGPI ERROR CKOUT LC89052T __________ UGPI is selected as an output pin during the clock switching transitional __________ UGPI . Low pulse is output when the output clock changes due to the Digital data Locked ...
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... To monitor interrupt source item 5 in the PLL locked state, the oscillator amplifier must be set to continuous operation mode, since the oscillator amplifier clock is used. When the LC89052T is set to the mode in which a H pulse is output from E/INT when an interrupt source occurs, the pulse width of each interrupt source is somewhere between 1/2 fs and 3/2 fs. ...
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... During readout, an application can stop providing CL input and set CE low and still have acquired the data read up to that point. For example, when reading the sub-code Q data, if the CRC flags are read and the data is found no good, there is no need to read the subsequent data. LC89052T CCB address B0 ...
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... Figure 9.4 Output Timing Chart (Normal high clock necessary to read DO0 with a port.) In the output timing shown in figure 9.4, data is allocated so that there are no problems even if the output register DO0 is not read. See the read register table for details. LC89052T DI0 ...
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... DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15 The shaded columns indicate reserved bits. Input 0 (zero) to these bits. LC89052T Table 9.4 Write Register Map 0xE8 0xE9 SYSRST GPISEL 0 GPIDAT PDOWN0 FLIMIT PDOWN1 FS4XIN PLLOPR FSSEL0 PLLCK0 ...
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... For systems that must minimize power consumption such as portable equipment, we recommend the PLLCK[1:0] = "00" (256fs) setting. For systems that require improved performance such as AV amplifiers, we recommend the PLLCK[1:0] = "10" (512fs) or PLLCK[1:0] = "11" (512/2fs) setting. LC89052T DI4 DI3 DI2 ...
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... Use the XIN clock as the source regardless of the PLL state. XISEL[3:0]: XIN input frequency setting 0000: 11.2896MHz (initial value) 0001: 12.288MHz 0010: 16.9344MHz 0011: Reserved 0001: 22.5792MHz 0010: 24.576MHz 0010: 33.8688MHz 0011: Reserved 1xxx: Must be set when the CKOUT pin and the XIN pin are connected. LC89052T No.7457-32/42 ...
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... LC89052T DI4 DI3 DI2 FSSEL0 FS4XIN FLIMIT DI12 DI11 DI10 ...
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... Mute the output in the PLL unlocked state. RDTSTA: DATAO output setting 0: Follow the RDTSEL setting. (initial value) 1: Output the SDIN data regardless of the PLL state. RDTMUT: DATAO mute setting 0: Output the data selected by RDTSEL. (initial value) 1: Mute the output. LC89052T No.7457-34/42 ...
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... When E/INT is set up with INTOPF for going to the high level when an interrupt is generated, the high level state is maintained until the interrupt source output (address 0xEB) is read out. When that data is read, the E/INT output returns to the normal low level. LC89052T DI4 DI3 ...
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... The channel status updated flag is computed by comparing the current data with the first 48 bits of the previous block. If those data are identical, the channel status is updated and the flag is output. LC89052T ______________ AUDIO pin state. ...
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... DO19 DO20 DO21 DO22 DO23 DO24 ….. DO54 DO55 DO56 ….. DO86 DO87 D00 and D01 (CRC) at chip address 0xED are loaded with the same value. LC89052T Table 9.8 Read Register Map 0xEB 0xEC 0 0 OUTERR OUTERR OUTPCM OUTPCM OUTEMP 0 OUTVFL FSCAL0 ...
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... Input fs calculation result not updated. 1: Input fs calculation result updated. OUTCSF: Updated result of first 48 bits of channel status (Cleared after read.) 0: Not updated. 1: Updated. OUTQSY: Detection of sub-code Q data readout load signal (Cleared after read.) 0: Not detected. 1: Detected. LC89052T DO4 DO3 DO2 OUTVFL OUTEMP OUTPCM DO1 DO0 OUTERR 0 No ...
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... It is also possible to read by using the updated flag of the interrupt source and setting E/INT to interrupt output to reduce the load of the microcontroller. This flag is output when the first 48 bits of the current data is compared with the data of the previous block and found that those data are identical. LC89052T DO4 DO3 ...
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... E/INT rising edge. The cyclic redundancy code (CRC set of flags that decide whether the 80 bits of sub-code Q data is correct. Note that the same data is loaded into both the DO0 and DO1 CRC flags. CRC Low High LC89052T DO4 DO3 DO2 0 0 ...
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... Application Example Decoupling capacitors (0.1 F) for the power supply pin, should be located as close to the LC89052T as possible. Use ceramic capacitors with good high frequency characteristics as the decoupling capacitors. Use a capacitor with a minimal thermal coefficient for the PLL loop filter capacitor. There are no constraints on the NC pin configuration. IC operation is not affected by leaving them open or by holding them fixed at particular levels ...
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... LC89052T PS No.7457-42/42 ...