tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 5

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

Advance Data Sheet, Rev. 2
July 2001
Features
STS12 Pointer Processor Features
STS1LT Features
STS1 XC Features
Agere Systems Inc.
Capable of detecting/inserting alarm indication sig-
nals (AIS), remote defect indication signals (RDI),
and remote error indication signals (REI).
Numerous monitoring functions provided on all the
TUG-3 path overhead bytes.
Supports unidirectional path switch ring (UPSR)
applications.
N1 tandem connection support is provided.
The TUG3 pointer processor can be used for an add/
drop multiplexer.
Complies with GR-253-CORE, T1.105, ITU-T G.707,
ITU-T G.831, G.783, ETS 300 417-1-1.
SONET and SDH compliant.
Configurable STS-3/STM-1 or STS-12/STM-4 mode.
Supporting an arbitrary mix of STS-1 and STS3c trib-
utaries, and SDH equivalents.
Complies with GR-253-CORE, T1.105, G.707,
G.783, G.806, G.821, and ETSI 417-1-1.
Supports standard SPE mappings for sub-STS-1
payloads (VT mapped: 28 DS1, 28 J1, or 21 E1 sig-
nals).
Supports standard SPE mappings for STS-1 pay-
loads ( DS3).
Detects STS-1 loss-of-signal (LOS) conditions.
Detects STS-1 out-of-frame and loss-of-frame (OOF/
LOF) conditions.
Provides an 8-bit parallel bus interface for an STS-1
signal.
Provides STS-1 selectable scrambler/descrambler
functions and B1/B2/B3 generation/detection.
Provides STS-1 pointer interpretation. Detects AIS-P
and LOP .
Provides STS-1 pointer processing.
Complies with GR-253-CORE, T1.105, G.707,
G.783, G.826, G.821, and ETSI 417-1-1.
Configurable connection for up to 6 STS1 signals
from 6 SPE mapper transmit blocks to any 1 up to
(continued)
TMXF84622 155 Mbits/s/622 Mbits/s Interface
3 STS1 slots of any 1 of 4 TMUX transmit interfaces.
Clock and control signals are provided by the TMUX
transmit interfaces and data is supplied by the SPE
mapper transmit blocks.
Configurable connection for up to 3 STS1 signals
from 3 STS1LT PP blocks to any 1 up to 3 STS1 slots
of any 1 of 4 TMUX transmit interfaces. Clock and
control signals are provided by the TMUX transmit
interfaces and data is supplied by the STS1LT
receive blocks.
Configurable connection for up to 12 STS1 signals
from the STS12PP transmit block to any 1 up to
3 STS1 slots of any 1 of 4 TMUX transmit interfaces.
Clock and control signals are provided by the TMUX
transmit interfaces and data is supplied by the
STS12PP transmit blocks.
Configurable connection for up to 9 STS1 signals
from 3 CDR receive blocks to any 1 up to 3 STS1
slots of any 1 of 4 TMUX transmit interfaces. Clock
and control signals are provided by the TMUX trans-
mit interfaces and data is supplied by the CDR
receive blocks.
Configurable connection for up to 3 STS1 signals
from 6 SPE mapper transmit blocks to any 1 of
3 STS1LT transmit blocks. Clock and control signals
are provided by the STS1LT transmit block and data
is supplied by the SPE mapper transmit block.
Configurable connection for up to 3 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 3 STS1LT transmit
blocks. Data is provided by the TMUX receive inter-
faces for this transfer.
Configurable connection for up to 9 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 3 CDR transmit blocks.
Clock, control signals, and data are provided by the
TMUX receive interfaces for this transfer.
Configurable connection for up to 3 STS1 signals
from 3 STS1LT receive blocks to any 1 of 6 SPE
mapper receive blocks. Clock, control signals, and
data are provided by the STS1LT receive block for
this transfer.
Configurable connection for up to 6 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 6 SPE mapper receive
blocks. Clock, control signals, and data are provided
by the TMUX receive interfaces for this transfer.
Loss of clock detectors on three serial 155 MHz clock
inputs from three CRD RX blocks and one serial
155 MHz clock input from CDR TX block.
SONET/SDH x84/x63 Ultramapper
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