tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 17

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper
The low-order path termination includes V5 byte termination, J2 path trace, Z6/N2 tandem connection, Z7/K4
enhanced RDI and low-order APS monitor, and the payload termination for asynchronous, byte- or bit-synchronous
signals. The V5 byte termination performs BIP-2 check (bit- or block-mode), REI count, RFI and RDI detection, sig-
nal label monitor, and automatic AIS insertion (which can be inhibited). The J2 monitor supports four different
modes as follows:
In byte-synchronous modes, the receive demapper generates a frame synchronization signal to indicate the DS1
frame bit or the MSB of the E1 time-slot 0. Additionally, it provides the framer access to the received signaling bits.
Output of the VT mapper is a DS1/J1/E1 signal with a gapped clock. It can be overwritten with AIS automatically or
upon microprocessor request.
2.11.2 Transmit Direction
In the transmit direction, the VT mapper gets a clock, data, and frame synchronization signal from the cross con-
nect. The input is retimed and checked for a digital loss of clock (LOC), an AIS condition, and low zeros density. In
byte-synchronous mode, the input signal is additionally checked for loss of frame synchronization (LOFS).
A transmit elastic store synchronizes the incoming DS1/J1/E1 signals to the local STS-1 clock. In asynchronous
and bit-synchronous mode, it works as a bit-oriented (64-bit) FIFO, and in byte-synchronous mode as a byte-wide
(8-byte) buffer using a V5 byte marker bit (8-bit). Overflow or underflow conditions are monitored and reported.
In asynchronous and bit-synchronous mode, a fixed VT pointer of 78 (VT1.5/TU-11) and 105 (VT2/TU-12) is gener-
ated and the payload is mapped into the container using positive/null/negative bit stuffing mechanism (C- and
S-bits). In bit-synchronous mode, the bit stuffing mechanism is disabled. In byte-synchronous mode, a dynamic VT
pointer value is generated using the V5 marker implementing NORM, NDF, INC, and DEC pointers.
The VT POH generation comprises V5 byte with BIP2-generation, AIS-, signal label-, UNEQ-insertion, automatic
REI-, RFI-, RDI-, and enhanced RDI-generation (Bellcore*, ITU-T), J2 path trace insertion via microprocessor,
Z6/N2 byte insertion, and Z7/K4 byte insertion via microprocessor or low-order path overhead (LOPOH) access
channel.
The data stream is synchronized to the received 2 kHz synchronization pulse and multiplexed to form the
STS-1/AU-3 signal, which is then output to the SPE mapper.
When operating in byte-synchronous mode, the phase and signaling bits from the framer are stored and inserted
into the mapped frame.
2.12 M13/M23 Multiplexer
The M13 is a highly-configurable multiplexer/demultiplexer. It can operate as an M13 in either the C-bit parity or
M23 mode, a mixed M13/M23, or an M23. In the C-bit parity mode, the M13 provides a far-end alarm and control
(FEAC) code generator and receiver, an HDLC transmitter and receiver, and automatic far-end block error (FEBE)
generation.
* Bellcore is now Telecordia TEchnologies, Inc.
Agere Systems Inc.
Cyclic check
SONET framing mode
SDH framing mode
Single byte check
(continued)
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
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