ax5031 AXSEM, ax5031 Datasheet - Page 18

• Manufacturer Part Number: ax5031
• Description: Datasheet Ax5031
• Manufacturer: AXSEM

18
Circuit Description
5.3.
The SYSCLK pin outputs the reference clock signal divided by a programmable integer.
Divisions from 1 to 2048 are possible. For divider ratios > 1 the duty cycle is 50%. Bits
SYSCLK[3:0] in the
5.4.
AX5031
After POR the
the
After POR or reset all registers are set to their default values.
5.5.
The RF frequency generation subsystem consists of a fully integrated synthesizer, which
multiplies the reference frequency from the crystal oscillator to get the desired RF frequency.
The advanced architecture of the synthesizer enables frequency resolutions of 1 Hz, as well as
fast settling times of 5 – 50 µs depending on the settings (see section 4.3: AC Characteristics).
Fast settling times mean fast start-up, which enables low-power system design.
The frequency must be programmed to the desired carrier frequency.
The synthesizer loop bandwidth can be programmed, this serves three purposes:
Version 1.3
1. Start-up time optimisation, start-up is faster for higher synthesizer loop bandwidths
2. TX spectrum optimisation, phase-noise at 300 kHz to 1 MHz distance from the carrier
3. Adaptation of the bandwidth to the data-rate. For transmission of FSK and MSK it is
PWRMODE
SYSCLK Output
Power-on-reset (POR)
RF Frequency Generation Subsystem
improves with lower synthesizer loop bandwidths
required that the synthesizer bandwidth must be in the order of the data-rate.
has an integrated power-on-reset block. No external POR circuit or signal is required.
AX5031
register.
PINCFG1
can be reset by SPI accesses, this is achieved by toggling the bit RST in
register set the divider ratio. The SYSCLK output can be disabled.
Datasheet AX5031