pa28f004sc-120 Intel Corporation, pa28f004sc-120 Datasheet - Page 16

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pa28f004sc-120

Manufacturer Part Number
pa28f004sc-120
Description
8-mbit 1-mbit X 8 Flashfiletm Memory
Manufacturer
Intel Corporation
Datasheet
28F008SA
16
FULL STATUS CHECK PROCEDURE
Figure 8 Automated Block Erase Flowchart
290429 – 8
290429 – 9
Standby Read
Repeat for subsequent bytes
Full status check can be done after each block or after a
sequence of blocks
Write FFH after the last block erase operation to reset the
device to Ready Array Mode
Operation
SR 3 MUST be cleared if set during a block erase attempt
before further attempts are allowed by the Write State
Machine
SR 5 is only cleared by the Clear Status Register
Command in cases where multiple blocks are erased
before full status is checked
If error is detected clear the Status Register before
attempting retry or other error recovery
Operation
Optional
Standby
Standby
Standby
Write
Write
Read
Bus
Bus
Command
Command
Erase
Setup
Erase
CPU may already have read
Status Register data in WSM
Ready polling above
Check SR 3
1
Check SR 4 5
Both 1
Error
Check SR 5
1
e
e
Data
Address
erased
Data
Address
erased
Check RY BY
V
Read Status Register
Check SR 7
1
Toggle OE
update Status Register
OH
e
V
Block Erase Error
PP
Ready 0
e
e
e
e
Low Detect
Ready V
Comments
Command Sequence
20H
D0H
Comments
e
e
Within block to be
Within block to be
or CE
or
e
OL
Busy
e
to
Busy

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