pa28f004sc-120 Intel Corporation, pa28f004sc-120 Datasheet - Page 12

• Manufacturer Part Number: pa28f004sc-120
• Description: 8-mbit 1-mbit X 8 Flashfiletm Memory
• Manufacturer: Intel Corporation

28F008SA
Write
Writes to the Command User Interface enable read-
ing of device data and Intelligent Identifiers They
also control inspection and clearing of the Status
Register Additionally when V
mand User Interface controls block erasure and byte
write The contents of the interface register serve as
input to the internal state machine
The Command User Interface itself does not occupy
an addressable memory location The interface reg-
ister is a latch used to store the command and ad-
dress and data information needed to execute the
command Erase Setup and Erase Confirm com-
mands require both appropriate command data and
an address within the block to be erased The Byte
Write Setup command requires both appropriate
command data and the address of the location to be
written while the Byte Write command consists of
the data to be written and the address of the loca-
tion to be written
The Command User Interface is written by bringing
WE
Addresses and data are latched on the rising edge
of WE
used
Refer to AC Write Characteristics and the AC Wave-
forms for Write Operations Figure 11 for specific
timing parameters
12
SR 2–SR 0
SR 7
SR 6
SR 5
SR 4
SR 3
1
0
1
0
1
0
1
0
1
0
to a logic-low level (V
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
Standard microprocessor write timings are
These bits are reserved for future use and
should be masked out when polling the Status
Register
WRITE STATE MACHINE STATUS
Ready
Busy
ERASE SUSPEND STATUS
Erase Suspended
Erase in Progress Completed
ERASE STATUS
Error in Block Erasure
Successful Block Erase
BYTE WRITE STATUS
Error in Byte Write
Successful Byte Write
V
V
V
PP
PP
PP
e
STATUS
Low Detect Operation Abort
OK
RESERVED FOR FUTURE
ENHANCEMENTS
WSMS
7
IL
PP
) while CE
ESS
6
e
Table 4 Status Register Definitions
V
PPH
ES
5
the Com-
is low
BWS
4
VPPS
COMMAND DEFINITIONS
When V
tions from the Status Register intelligent identifiers
or array blocks are enabled Placing V
enables successful byte write and block erase oper-
ations as well
Device operations are selected by writing specific
commands into the Command User Interface Table
3 defines the 28F008SA commands
Read Array Command
Upon initial device powerup and after exit from deep
powerdown mode the 28F008SA defaults to Read
Array mode This operation is also initiated by writing
FFH into the Command User Interface Microproces-
sor read cycles retrieve array data The device re-
mains enabled for reads until the Command User
Interface contents are altered Once the internal
Write State Machine has started a block erase or
byte write operation the device will not recognize
the Read Array command until the WSM has com-
pleted its operation The Read Array command is
functional when V
NOTES
RY BY
be checked to determine byte write or block erase com-
pletion before the Byte Write or Erase Status bit are
checked for success
If the Byte Write AND Erase Status bits are set to ‘‘1’’s
during a block erase attempt an improper command se-
quence was entered Attempt the operation again
If V
cleared before another byte write or block erase opera-
tion is attempted
The V
provide continuous indication of V
terrogates the V
erase command sequences have been entered and in-
forms the system if V
V
back between V
3
PP
PP
Status bit is not guaranteed to report accurate feed-
low status is detected the Status Register must be
PP
PPL
or the Write State Machine Status bit must first
Status bit unlike an A D converter does not
R
2
is applied to the V
PP
PPL
level only after the byte write or block
and V
PP
R
1
PP
e
has not been switched on The
PPH
V
PPL
R
0
or V
PP
PP
level The WSM in-
PPH
pin read opera-
PPH
on V
PP