mt58l512y36d Micron Semiconductor Products, mt58l512y36d Datasheet - Page 6

• Manufacturer Part Number: mt58l512y36d
• Description: 16mb 1 Meg X 18, 512k X 32/36 Pipelined, Dcd Syncburst Sram
• Manufacturer: Micron Semiconductor Products

TQFP PIN DESCRIPTIONS (continued)
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
62, 63, 68, 69, 56-59, 62, 63
13, 18, 19, 22, 72-75, 78, 79
26, 40, 55, 60, 26, 40, 55, 60,
66, 75, 78, 79,
54, 61, 70, 77 54, 61, 70, 77
67, 71, 76, 90 67, 71, 76, 90
16, 25, 28-30,
51-53, 56, 57,
4, 11, 20, 27,
5, 10, 17, 21,
1-3, 6, 7, 14
(b)
15, 41, 65,
(a)
72, 73
38, 39
95, 96
8, 9, 12,
x18
58, 59,
NA
84
85
31
23
74
24
91
–
–
22-25, 28, 29
4, 11, 20, 27,
5, 10, 17, 21,
(c)
15, 41, 65,
(a)
(d)
14, 16, 66
(b)
x32/x36
12, 13
38, 39
2, 3, 6-9,
52, 53,
18, 19,
NA
68, 69
84
85
31
51
80
30
91
1
SYMBOL TYPE
NC/DQPb
NC/DQPd
NC/DQPa
NC/DQPc
ADSP#
ADSC#
(LBO#)
MODE
V
DNU
DQa
DQb
DQd
DQc
V
V
NC
NF
DD
DD
SS
Q
Output DQa pins; Byte “b” is associated with DQb pins. For the x32 and
Supply Power Supply: See DC Electrical Characteristics and Operating
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Supply Ground: GND.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with
Input
Input
Input
NC/
I/O
–
–
–
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating. LBO# is
the JEDEC-standard term for MODE.
x36 versions, Byte “a” is associated with DQa pins; Byte “b” is
associated with DQb pins; Byte “c” is associated with DQc pins;
Byte “d” is associated with DQd pins. Input data must meet setup
and hold times around the rising edge of CLK.
No Connect/Parity Data I/Os: On the x32 version, these pins are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;
Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is
DQPd.
Conditions for range.
Operating Conditions for range.
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
No Function: These pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to leave these
pins unconnected or driven by signals.
Synchronous Address Status Processor: This active LOW input
Synchronous Address Status Controller: This active LOW input
Mode: This input selects the burst sequence. A LOW on this pin
PIPELINED, DCD SYNCBURST SRAM
6
16Mb: 1 MEG x 18, 512K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2000, Micron Technology, Inc.
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