as4c8m16s Alliance Memory, Inc, as4c8m16s Datasheet - Page 46
as4c8m16s
Manufacturer Part Number
as4c8m16s
Description
128mb/ 8m X 16 Bit Synchronous Dram Sdram
Manufacturer
Alliance Memory, Inc
Datasheet
1.AS4C8M16S.pdf
(52 pages)
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Figure 37. Full Page Write Cycle
A0-A9,
A11
CS#
CLK
CKE
RAS#
CAS#
WE#
A10
DQM
DQ
BA0,1
FEBRUARY 2011
Hi-Z
Activate
Cammand
Bank A
High
RAx
RAx
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Write
Command
Bank A
CAx
DAx
DAx+1 DAx+2 DAx+3 DAx-1
Activate
Cammand
Bank B
RBx
The burst counter wraps
from the highest order
page address back to zero
during this time interval
RBx
(Burst Length=Full Page)
DAx
DAx+1
Write
Command
Bank B
Full Page burst operation does not
terminate when the burst length is
satisfied; the burst counter increments
and continues bursting beginning with
the starting address
CBx
DBx
46
DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Stop
Command
Precharge
Command
Bank B
Data is ignored
Don’t Care
Activate
Command
Bank B
RBy
RBy
AS4C8M16S
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