ia3513 integration, ia3513 Datasheet - Page 27

• Manufacturer Part Number: ia3513
• Description: Headset Voice And Power Solution
• Manufacturer: integration

Application Example 2 - Sticky Mode and Interruption Handling
To better illustrate how the sticky mode and the interruption should be handled the next example is depicted.
The following GPIO configuration is assumed:
•
•
•
The interrupt notification bits INT, DDB and LB of the register 11 can only be changed (cleared) by writing a ‘0’. When writing ‘1’,
their status remains unchanged. The GPS1 bit, because is configured as a sticky bit, behaves in the same way.
The GPIO5 can not be changed because it is an output, and is controlled by the interruption notification logic.
So if there is the need to change the GPIO 2, 3, or 4 output values, without disturbing the interrupt, and the sticky bits statuses,
the safe value to be written to the register 11 (GPIO status and interruption handling register) is: “1 1 1 1 GPS2 GPS3 GPS4 1”,
where the GPSx values are the new values for the GPIO configured as outputs.
Application Example 3 – Interruption Notification, Single Register
The recommended way to handle interruptions generated by the GPIO pins is to configure the corresponding bits in register 15
as sticky bits. In this way a status is kept on the interruption source, since the bit remains high (sticky) even if the signal at the
GPIO pin changes its value. In the following example it is illustrated what happens when a new interruption is generated before
an old one is acknowledged.
The following GPIO configuration is assumed:
•
•
Then this chain of events takes place:
GPIO 1 - input, interruption unmasked, and sticky mode enabled for button handling
GPIO 2, 3 and 4 - outputs, open drain
GPIO 5 - output, interruption notification
GPIO 2 and 3 - inputs, with sticky mode enabled, and with interruption generation enabled (register 16)
GPIO 5 - output, interruption notification
1)
2)
3)
4)
5)
6)
7)
GPIO2 goes high, triggering an interruption.
GPIO5 goes high because it is configured for interrupt notification.
The host receives the interrupt request a proceeds to read register 11 (GPIO - Status and Interruption Handling) to
determine the triggering event. I detects that GPS2 bit is high, thus it is responsible for the interrupt.
While the ISR runs on the host a new interrupt is generated on GPIO3.
After the ISR finishes handling the GPIO2 interruption, it proceeds to acknowledge it, by clearing bits INT and GPS2 in
register 11. Because there is another pending interrupt in GPIO3, the GPIO5 interrupt notification pin is pulsed low like
it is illustrated in the next figure (the size of this pulse is one SCL clock cycle):
The host detects a new interruption due to the pulse action on GPIO5 a proceeds to read register 11 again. It detects
that GPS3 bit is high, thus it is responsible for this new interrupt.
After the ISR finishes handling the GPIO2 interruption, it proceeds to acknowledge it, by clearing bits INT and GPS3 in
register 11. Because there is no other pending interrupt, the GPIO5 interrupt notification pin goes low as illustrated in
the next figure:
GPIO5
SDA
SCL
START
START
SAD6
AD0
slave
ACK
INT
DDB
LB
GPS1
GPS2
GPS3
GPS4
GPS5
slave
ACK
STOP
STOP
IA3513
27