ia3513 integration, ia3513 Datasheet - Page 21

• Manufacturer Part Number: ia3513
• Description: Headset Voice And Power Solution
• Manufacturer: integration

IA3513
I2C Interface
Description
The I2C-IF block is configured to act as a slave device hanging on a standard I2C bus version 2.1. This bus uses a two wire only
interface, with bidirectional clock and data lines. All devices hanging on the I2C bus (either masters or slaves) should only drive
it using open drain (or alike) transceivers, which results in a wired-AND functionality when multiple devices try to drive the bus
simultaneously.
The I2C address of the IA3513 is 1001111.
The clock stretching functionality isn’t implemented in this slave, since it is not needed, because this is a relatively fast device.
Thus, the SCL clock line can be considered as input only for this slave.
The SDA line is bidirectional and is both sampled, and driven by this slave. When driving the SDA line this slave only forces it low,
relying on an external resistor to pull the line high.
Start and Stop conditions
Normally the SDA line is only allowed to change state when the SCL line is low. Whenever the SDA line transitions during SCL
high, it is interpreted as a start or a stop condition, depending on the direction of the change: falling for a start condition, or
rising for a stop condition.
Acknowledge
All 8 bit transfers either from master to slave, or the other way around, are terminated by an acknowledge bit (active low) driven
by the receiving device.
Protocol Reset
As a failsafe mechanism, whenever there is a failure in the protocol (power loss, system reset, and so on) the slave can be reset
by applying the following sequence:
1) Clock up to 9 cycles
2) Look for SDA high
3) Create start condition and slave will start listening for its slave address, or create stop condition and slave will go to the idle
state (will wait for a new start condition)
Write operations
Random write
To perform a random write to a register, two words must be sent to the slave (after it has received the proper slave address). The
first 8 bit word contains the address of the register that will be written. The following 8 bit word contains the data to write into
the register. To end the random write, the master then sends a stop condition.
Sequential write
By starting with a random write, if the master keeps clocking in data words (8 bits each), then the address register keeps getting
incremented and the data is written into the following registers in sequence. The slave always acknowledges each byte written
(even if to invalid registers), as this indicates that the data was received properly (and not that was stored into a register). The
current address rolls over from 255 to 0.
Read operations
Random read
To start a random register read, the master first starts with a dummy write cycle, specifying the address to be read. After sending
the register address word (8 bits), a repeated start is generated and a read cycle follows, returning the contents of the
addressed register. The master then does not acknowledge the read (acknowledge bit high), and follows with a stop condition,
thus ending the cycle.
Sequential read
After some other read operation (random or current address read), if the master continues to acknowledge the read
(acknowledge bit low) and clocking the slave’s data out, then the address register keeps getting incremented and the registers
are read in sequence until the master stops acknowledging and sends a stop condition. The register address is incremented by
1 every time the master acknowledges a read, and will roll over from 255 to 0 (this means that after reading the last valid
register address, garbage will be read until the roll over happens).
21