k9f4g08u0m-y Samsung Semiconductor, Inc., k9f4g08u0m-y Datasheet - Page 34

• Manufacturer Part Number: k9f4g08u0m-y
• Description: 512m X 8 Bits / 1g X 8 Bits Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9K8G08U1M
K9F4G08U0M
Figure 12. Page Copy-Back program Operation with EDC & Read EDC Status
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
Two-Plane Page Program
Two-Plane Page Program is an extension of Page Program, for a single plane with 2112 byte page registers. Since the device is
equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two
pages.
After writing the first set of data up to 2112 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B
remains in Busy state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device
returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the
81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy
Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the
same as that of Page Program. Althougth two planes are programmed simultaneously, pass/fail is not available for each page when
the program operation completes. Status bit of I/O 0 is set to "1" when any of the pages fails.
Restriction in addressing with Two-Plane Page Program is shown is Figure14.
EDC OPERATION
Note that the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during
Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data
input at the same address.
R/B
I/Ox
R/B
I/Ox
00h
60h
Col. Add.1,2 & Row Add.1,2,3
Source Address
Add.(5Cycles)
Address Input(3Cycle)
Row Add 1,2,3
18
to A
35h
29
is valid while A
t
R
85h
Col. Add.1,2 & Row Add.1,2,3
D0h
12
Destination Address
to A
Add.(5Cycles)
17
34
is ignored. The Erase Confirm command(D0h) following the block
t
BERS
10h
t
PROG
70h
FLASH MEMORY
7Bh
EDC Status Output
I/O
Fail
Advance
0
"1"
"0"
Pass