k9f4g08u0m-y Samsung Semiconductor, Inc., k9f4g08u0m-y Datasheet - Page 33

• Manufacturer Part Number: k9f4g08u0m-y
• Description: 512m X 8 Bits / 1g X 8 Bits Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

Figure 10. Page Copy-Back program Operation
Copy-Back Program
The Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-
efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-
ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves
the whole 2,112-byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input com-
mand (85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to
actually begin the programming operation. During tPROG, the device executes EDC of itself. Once the program process starts, the
Read Status Register command (70h) or Read EDC Status command (7Bh) may be entered to read the status register. The system
controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register.
When the Copy-Back Program is complete, the Write Status Bit(I/O 0) and EDC Status Bits (I/O 1 ~ I/O 4) may be checked(Figure 10
& Figure 11& Figure 12). The internal write verification detects only errors for "1"s that are not successfully programmed to "0"s and
the internal EDC checks whether there is only 1-bit error for each 528-byte plane of the source page. More than 2-bit error detection
is not available for each 528-byte plane. The command register remains in Read Status command mode or Read EDC Status com-
mand mode until another valid command is written to the command register.
During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11. But EDC
status Bits are not available during copy back for some bits or bytes modified by Random Data Input operation.
However, in case of the 528 byte plane unit modification, EDC status bits are abailable.
Figure 11. Page Copy-Back program Operation with Random Data Input
K9K8G08U1M
K9F4G08U0M
Figure 9. Random Data Input In a Page
R/B
I/Ox
R/B
I/Ox
R/B
I/Ox
Note
80h
Note: 1. For EDC operation, only one time random data input is possible at the same address.
00h
00h
:
Col. Add.1,2 & Row Add1,2,3
1. Copy-Back Program operation is allowed only within the same memory plane.
2. On the same plane, It’s prohibited to operate copy-back program from an odd address page(source page) to an even
address page(target page) or from an even address page(source page) to an odd address page(target page).
Therefore, the copy-back program is permitted just between odd address pages or even address pages.
Col. Add.1,2 & Row Add.1,2,3
Col. Add.1,2 & Row Add.1,2,3
Address & Data Input
Source Address
Source Address
Add.(5Cycles)
Add.(5Cycles)
Data
35h
35h
85h
t
R
t
R
85h
Address & Data Input
Col. Add.1,2 & Row Add.1,2,3
85h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
Col. Add.1,2
Add.(5Cycles)
Data
Destination Address
Add.(5Cycles)
33
Data
10h
10h
There is no limitation for the number of repetition.
85h
t
PROG
t
Col. Add.1,2
Add.(2Cycles)
PROG
FLASH MEMORY
70h
70h
Data
10h
I/O
Fail
I/O
Fail
0
"1"
Advance
0
t
PROG
"0"
70h
Pass
Pass