ppc460ex Applied Micro Circuits Corporation (AMCC), ppc460ex Datasheet - Page 12

• Manufacturer Part Number: ppc460ex
• Description: Powerpc 460ex Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

460EX – PPC460EX Embedded Processor
Security Function (optional)
The built-in security function (PPC460EX-S only) is a cryptographic engine attached to the PLB with built-in DMA
and interrupt controllers.
Features include:
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• AHB
• OPB
• DCR
• Federal Information Processing Standard (FIPS) 140-2 design
• Support for an unlimited number of Security Associations (SA)
• Different SA formats for each supported protocol (IPsec/SSL/TLS/sRTP)
• Internet Protocol Security (IPSec) features
• Secure Socket Layer (SSL) and Transport Layer Security (TLS) features
• Secure Real-Time Protocol (sRTP) features
• IPsec/SSL security acceleration engine
• DES, 3DES, AES, ARC-4, AES-GCM, and GMAC-AES encryption
• MD-5, SHA-1, and SHA-256 hashing, HMAC encrypt-hash and hash-decrypt with KASUMI
• Public key acceleration for RSA, DSA and Diffie-Hellman
• True or pseudo random number generators
• Interrupt controller
• DMA controller
– 200MHz, maximum 12.8GB/s (simultaneous read and write)
– Processor:bus clock ratios of N:1
– 32-bit data path
– 32-bit address
– Synchronous to the PLB
– Up to 200MHz, maximum 800MB/s
– 32-bit data path with dynamic sizing for 32-, 16-, and 8-bit width
– 32-bit address
– 100MHz
– 32-bit data path
– 10-bit address
– Full packet transforms (ESP & AH)
– Complete header and trailer processing (IPv4 and IPv6)
– Multi-mode automatic padding
– "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
– Packet transforms
– One-pass hash-then-encrypt for SSL and TLS packet transforms for inbound packet using Stream Cipher
– Packet transforms
– ROC removal and TAG insertion
– Variable bypass offset of header length per packet
– Non-deterministic true random numbers
– Pseudo random numbers with lengths of 8B or 16B
– ANSI X9.17 Annex C compliant using a DES algorithm
– Fifteen programmable, maskable interrupts
– Initiate commands via an input interrupt
– Sixteen programmable interrupts indicating completion of certain operations
– All interrupts mapped to one level- or edge-sensitive programmable interrupt output
– Autonomous, 4-channel
– 1024-words (32 bits/word) per DMA transfer
– Scatter/gather capability with byte aligned addressing
Preliminary Data Sheet
Revision 1.12 – July 17, 2008
AMCC Proprietary