ppc440gr-3jb667cz Applied Micro Circuits Corporation (AMCC), ppc440gr-3jb667cz Datasheet - Page 71

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ppc440gr-3jb667cz

Manufacturer Part Number
ppc440gr-3jb667cz
Description
Powerpc 440gr Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
Table 19. Peripheral Interface Clock Timings (Continued)
Figure 6. Input Setup and Hold Waveform
AMCC Proprietary
440GR – PPC440GR Embedded Processor
EMCRxClk input high time
EMCRxClk input low time
PerClk (and OPB Clock) output frequency (for ext. master or
sync. slaves)
PerClk period
PerClk output high time
PerClk output low time
UARTSerClk input frequency
UARTSerClk period
UARTSerClk input high time
UARTSerClk input low time
TmrClk1 input frequency
TmrClk1 period
TmrClk1 input high time
TmrClk1 input low time
Notes:
1. T
2. In RMII mode, 50MHz +/- 50PPM input EMCRefClk is required. In SMII mode, a 125 MHz +/- 100PPM input EMCRefClk is required.
Clock
Inputs
frequency is 66.66 MHz.
OPB
is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock
1.25V
Parameter
T
IS
min
35% of nominal period
35% of nominal period
50% of nominal period
33% of nominal period
40% of nominal period
40% of nominal period
Valid
2T
T
T
33.33
OPB
OPB
Min
OPB
15
10
+1
+1
+2
T
IH
min
66% of nominal period
50% of nominal period
60% of nominal period
60% of nominal period
1000 / (2T
Preliminary Data Sheet
Revision 1.19 – May 07, 2008
66.66
Max
100
30
OPB
1
+2ns)
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
1
2
71

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