ppc440gr-3jb667cz Applied Micro Circuits Corporation (AMCC), ppc440gr-3jb667cz Datasheet - Page 13

• Manufacturer Part Number: ppc440gr-3jb667cz
• Description: Powerpc 440gr Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

External Peripheral Bus Controller (EBC)
Features include:
Ethernet Controller Interface
Ethernet support provided by the PPC440GR interfaces to the physical layer but the PHY is not included on the
chip:
DMA to PLB3 Controller
This DMA controller provides a DMA interface between the OPB and the 64-bit PLB.
Features include:
AMCC Proprietary
440GR – PPC440GR Embedded Processor
• Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 66.66MHz operation
• Burst and non-burst devices
• 16-bit byte-addressable data bus
• 30-bit address
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
• Programmable address mapping
• External DMA Slave Support
• External master interface
• One to two 10/100 interfaces running in full- and half-duplex modes
• Supports the following transfers:
• Four channels
• Scatter/Gather capability for programming multiple DMA operations
• 32-byte buffer
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 32-bit addressing
• Address increment or decrement
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
– 256 Wait States for non-burst
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
– Write posting from external master
– Read prefetching on PLB for external master reads
– Bursting capable from external master
– Allows external master access to all non-EBC PLB slaves
– External master can control EBC slaves for own access and control
– One full Media Independent Interface (MII) with 4-bit parallel data transfer
– Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer
– Two Serial Media Independent Interfaces (SMII)
– Packet reject support
– Memory-to-memory transfers
– Buffered peripheral to memory transfers
– Buffered memory to peripheral transfers
Preliminary Data Sheet
Revision 1.19 – May 07, 2008
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