psd511b1 STMicroelectronics, psd511b1 Datasheet - Page 63

• Manufacturer Part Number: psd511b1
• Description: Low Cost Field Programmable Microcontroller Peripherals
• Manufacturer: STMicroelectronics

Power
Management
Unit
(Cont.)
60
PSD5XX Family
Table 17. Power Management Mode Registers (PMMR0, PMMR1)
Bit 0
Bit 1 0 = ALE Power Down (PD) Polarity Low.
Bit 2 0 = Automatic Power Down (APD) Disable.
Bit 3 0 = EPROM/SRAM CMiser is OFF.
Bit 4 0 = ZPLD Turbo is ON. ZPLD is always ON.
Bit 5 0 = ZPLD Clock Input into the Array from the CLKIN pin input is connected. Every
Bit 6 0 = ZPLD Clock Input into the the MacroCell registers from the CLKIN pin input
Bit 7 0 = In the PSD5XX Clock Input is connected to the Timer.
Bit 0
Bit 1
Bit 2–7 0 = Reserved for future use, should be set to zero.
Table 18. APD Counter Operation
PMMR1
PMMR0
TMR CLK
1 = OFF
APD EN Bit
Bit 7
Bit 7
*
*
1 = ALE Power Down (PD) Polarity High.
1 = Automatic Power Down (APD) Enable.
1 = EPROM/SRAM CMiser is ON.
1 = ZPLD Turbo is OFF. ZPLD will Power Down when inputs are not changing.
1 = ZPLD Clock Input into the Array from the CLKIN pin input is disconnected.
1 = ZPLD Clock Input into the the MacroCell registers from the CLKIN pin input
1 = In the PSD5XX Clock Input is disconnected from the Timer.
= Should be set to High (1) to operate the APD.
0
1
1
1
0 = Automatic Power Down Unit Clock is connected to Port E7 (PE7) alternate
1 = Automatic Power Down Unit Clock is connected to the PSD Clock
0 = Sleep Mode Disabled.
1 = Sleep Mode Enabled.
Clock change will Power Up the ZPLD when Turbo bit is OFF.
is connected.
is disconnected.
function input.
input (CLKIN).
1 = OFF
RCLK
ZPLD
Bit 6
Bit 6
*
Down Polarity
ALE Power
1 = OFF
ACLK
ZPLD
Bit 5
Bit 5
X
X
1
0
*
1 = OFF
TURBO
ZPLD
Bit 4
Bit 4
*
ALE Status
Pulsing
X
1
0
CMISER
1 = ON
Bit 3
Bit 3
*
ENABLE
Not Counting
Not Counting
Counting (Activates Standby
Mode After 15 Clocks)
Counting (Activates Standby
Mode After 15 Clocks)
1 = ON
Bit 2
Bit 2
APD
*
APD Counter
1 = HIGH
ALE PD
1 = ON
Polarity
Sleep
Mode
Bit 1
Bit 1
1 = CLKIN
APD CLK
Bit 0
Bit 0
*