psd511b1 STMicroelectronics, psd511b1 Datasheet - Page 14

• Manufacturer Part Number: psd511b1
• Description: Low Cost Field Programmable Microcontroller Peripherals
• Manufacturer: STMicroelectronics

9.0
The PSD5XX
Architecture
PSD5XX consists of seven major functional blocks:
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable. The chip configurations are specified
by the user in the PSDsoft Development Software; some are specified by setting up the
appropriate bits in the configuration registers during run time.
9.1 ZPLD Block
Key Features
General Description
The ZPLD block has 3 embedded PLD devices:
Figure 4 shows the architecture of the ZPLD. The PLD devices all share the same
input bus. The true or complement of the 61 input signals are fed to the programmable
AND-ARRAY. Names and source of the input signals are shown in Table 3. The PA, PB, PE
signals, depending on user configuration, can either be macrocell feedbacks or inputs from
Port A, B or E.
ZPLD Blocks
Bus Interface
I/O Ports
Memory Block
Power Management Unit
Counter/Timer
Interrupt Controller
3 Embedded ZPLD devices
Maximum 30 macrocells
Combinatorial/registered outputs
Maximum 140 product terms
Programmable output polarity
User configured register clear/preset
User configured register clock input
61 Inputs
Accessible via 24 I/O pins
Power Saving Mode
UV-Erasable
Generate user defined interrupts to Interrupt Controller
and controls to Counter/ Timer
DPLD
The Address Decoding PLD, generating select signals to internal I/O or memory blocks.
GPLD
The General Purpose PLD provides 24 programmable macrocells for general or
complex logic implementation; dedicated to user application.
PPLD
The Peripheral PLD, includes 6 programmable macrocells. The PPLD provides control
to the operation of the Counter/Timer and Interrupt Controller.
PSD5XX Family
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