saa5647hl NXP Semiconductors, saa5647hl Datasheet - Page 38

• Manufacturer Part Number: saa5647hl
• Description: Saa56xx Enhanced Tv Microcontrollers With On-screen Display Osd
• Manufacturer: NXP Semiconductors

Philips Semiconductors
10 POWER SAVING MODES OF OPERATION
Three power saving modes are incorporated in the
SAA56xx device: Standby, Idle and Power-down. When
utilizing one of these modes, power to the device (V
V
is achieved by clock gating on a section-by-section basis.
10.1
During Standby mode, the Acquisition and Display
sections of the device are disabled. The following
functions remain active:
To enter Standby mode, the STANDBY bit in the
ROMBK register must be set. Once in Standby, the crystal
oscillator continues to run, but the internal clocks to
Acquisition and Display are gated out. However, the clocks
to the 80C51 CPU Core, Memory Interface, I
UART, Timer/counters, Watchdog Timer and Pulse Width
Modulators are maintained. Since the output values on
RGB and VDS are maintained, the display output must be
disabled before entering this mode.
The Standby mode may be used in conjunction with both
Idle and Power-down modes. Hence, prior to entering
either Idle or Power-down, the STANDBY bit may be set,
thus allowing wake-up of the 80C51 CPU core without fully
waking the entire device. (This enables detection of a
Remote Control source in a power saving mode.)
10.2
During Idle mode, Acquisition, Display and the
CPU sections of the device are disabled. The following
functions remain active:
To enter Idle mode, bit IDL in the PCON register must be
set. The Watchdog Timer must be disabled prior to
entering Idle to prevent the device being reset.
2004 Sep 03
DDC
80C51 CPU Core
Memory interface
I
Timer/counters
Watchdog Timer
UART, SAD, PWMs.
Memory interface
I
Timer/counters
Watchdog Timer
UART, SAD, PWMs.
Enhanced TV microcontrollers with
On-Screen Display (OSD)
2
2
C-bus interface
C-bus interface
and V
Standby mode
Idle mode
DDA
) should be maintained, since power saving
2
C-bus,
DDP
,
38
Once in Idle mode, the crystal oscillator continues to run,
but the internal clock to the CPU, Acquisition and Display
are gated out. However, the clocks to the Memory
Interface, I
Pulse Width Modulators are maintained. The CPU state is
frozen along with the status of all SFRs. Internal
RAM contents are maintained, as are the device output pin
values. Since the output values on RGB and VDS are
maintained, the Display output must be disabled before
entering this mode.
There are three methods available to recover from Idle:
10.3
In Power-down mode, the crystal oscillator is stopped. The
contents of all SFRs and Data memory are maintained,
however, the contents of the Auxiliary/Display memory are
lost. The port pins maintain the values defined by their
associated SFRs. Since the output values on RGB and
VDS are maintained, the Display output must be made
inactive before entering Power-down mode.
The Power-down mode is activated by setting bit PD in the
PCON register. It is advisable to disable the Watchdog
Timer prior to entering Power-down. Recovery from
Power-down takes several milliseconds as the oscillator
must be given time to stabilize.
Assertion of an enabled interrupt will cause bit IDL to be
cleared by hardware, thus terminating Idle mode. The
interrupt is serviced and, following the instruction RETI,
the next instruction to be executed will be the one after
the instruction that put the device into Idle mode.
A second method of exiting Idle is via an interrupt
generated by the SAD DC Compare circuit. When the
SAA56xx is configured in this mode, detection of an
analog threshold at the input to the SAD may be used to
trigger wake-up of the device i.e. TV Front Panel
Key-press. As above, the interrupt is serviced, and
following the instruction RETI, the next instruction to be
executed will be the one following the instruction that put
the device into Idle.
The third method of terminating Idle mode is with an
external hardware reset. Since the oscillator is running,
the hardware reset need only be active for 24 crystal
clocks at 12 MHz to complete the reset operation. Reset
defines all SFRs and Display memory to a pre-defined
state, but maintains all other RAM values. Code
execution commences with the Program Counter set to
‘0000’.
Power-down mode
2
C-bus, Timer/counters, Watchdog Timer and
Product specification
SAA56xx