mt9v112 Micron Semiconductor Products, mt9v112 Datasheet - Page 39

• Manufacturer Part Number: mt9v112
• Description: 1/6-inch Soc Vga Cmos Digital Image Sensor
• Manufacturer: Micron Semiconductor Products

T able 12: Sensor Core Register Descriptions (continued)
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
Bit 5
Reset SOC
Bit 4
Output
Disable
Bit 3
Chip Enable
Bit 2
Standby
Bit 1
Restart
Bit 0
Reset
R32:0—0x020 – Read Mode—Context B
Bit 15
XOR Line
Valid
Bit 14
Continuous
Line Valid
Bit 10
Low-Power
Mode—
Context B
Bit 9
Show
Border
Bit 8
Over Sized
Bits 7:6
Bit 5
Column
Skip 4x
Bit 4
Row Skip 4x
BIT FIELD
This reset signal is fed directly to the SOC part of the chip, and
has no functionality in a stand alone sensor.
When set, the output signals are tri-stated.
0: Stop sensor readout.
When this is returned to “1,” sensor readout restarts and begins
resetting the starting row in a new frame. To reduce the digital
power, the master clock to the sensor can be disabled or
ST ANDBY can be used.
1: Normal operation.
0: Normal operation (default)
1: Disable analog circuitry and internal clocks. Whenever this bit
is set to “ 1” the chip enable bit (bit 3) should be set to “0.”
Setting this bit causes the sensor to abandon the current frame
and start resetting the first row. The delay before the first valid
frame is read out equals the integration time. This bit always
reads “0.”
Setting this bit puts the sensor in reset mode; this sets the sensor
to its default power-up state. Clearing this bit resumes normal
operation.
0: LINE_VALID determined by bit 9.
Ineffective if Continuous LINE_VALID is set.
1: LINE_VALID = “Continuous” Line Valid XOR Frame Valid,
0: Normal LINE_VALID (default, no line valid during vertical
blanking).
1: “Continuous” LINE_VALID (continue producing line valid
during vertical blanking).
When READ mode context B is selected (bit 3, Reg0x0C8 = 1):
0: Full power, maximum readout speed.
1: Low power. Maximum readout frequency is now half of the
master clock, and the pixel clock is automatically adjusted as
described for the pixel clock speed register.
This bit indicates whether to show the border enabled by bit 8.
When bit 8 is 0, this bit has no meaning. When bit 8 is 1, this bit
decides whether the border pixels should be treated as extra
active pixels (1) or extra blanking pixels (0).
When this bit is set, a 4-pixel border is output around the active
image array independent of readout mode (skip, zoom, mirror,
etc.). Setting this bit therefore adds eight to the numbers of
rows and columns in the frame.
Reserved.
0: Normal readout.
1: READ out two columns, and then skip six columns (as with
rows).
0: Normal readout.
1: READ out two rows, and then skip six rows (i.e., row 8, row 9,
row 16, row 17…).
DESCRIPTION
39
SOC VGA DIGITAL IMAGE SENSOR
Micron Technology, Inc., reserves the right to change products or specificat ions wit hout not ice.
DEFAULT
(HEX)
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x1
0x0
0x0
0x0
SYNC’D TO
FRAME
START
©2004 Micron Technology, Inc. All rights reserved.
N
N
N
N
N
N
N
N
Y
N
Y
Y
Y
Y
PRELIMINARY
MT9V112
FRAME
BAD
YM
YM
YM
YM
YM
YM
YM
YM
YM
0
0
0
0
0
WRITE
READ/
W
W
W
W
W
W
W
W
W
W
W
W
W
W