mt9v112 Micron Semiconductor Products, mt9v112 Datasheet - Page 38

• Manufacturer Part Number: mt9v112
• Description: 1/6-inch Soc Vga Cmos Digital Image Sensor
• Manufacturer: Micron Semiconductor Products

T able 12: Sensor Core Register Descriptions (continued)
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
Bits 7:4
Delay Pixel
Clock
Bits 3:0
Pixel Clock
Speed
R11:0—0x00B – Extra Delay
Bits 13:0
Extra Delay
R12:0—0x00C – Shutter Delay
Bits 10:0
Shutter
Delay
R13:0—0x00D – Reset
Bit 15
Synchronize
Changes
Bit 13
Stop_soc
Bit 12
Div 2
Bit 10
Switch
Two-wire
Interface ID
Bit 9
Restart Bad
Frames
Bit 8
Show Bad
Frames
Bit 7
Inhibit
Standby
Bit 6
Drive
Signals
BIT FIELD
Delay PIXCLK in half-master-clock cycles. When set, the pixel
clock can be delayed in increments of half-master- clock cycles
compared to the synchronization of FRAME_VALID, LINE_VALID,
and DATA_OUT.
The pixel clock period is doubled, so the ADC clock period
remains the same for one programmed register value. The value
“0” is not allowed, and “1” is used instead.
Extra blanking inserted between frames specified in pixel clocks.
Can be used to get a more exact frame rate. For integration
times less than a frame, however, it might affect the integration
times for parts of the image.
The amount of time from the end of the sampling sequence to
the beginning of the pixel reset sequence. This variable is
automatically halved in low-power mode, so the time in use
remains the same. This register has an upper value defined by
the fact that the reset needs to finish prior to readout of that
row to prevent changes in the row time.
0: Normal operation, updates changes to registers that affect
image brightness at the next frame boundary (integration time,
integration delay, gain, horizontal blanking and vertical
blanking, window size, row/column skip, or row mirror.
1: Do not update any changes to these settings until this bit is
returned to “0.” All registers that are frame-synchronized are
affected by this bit setting.
Setting this bit turns off all SOC clocks.
By setting this bit, the CLK_IN is divided by two before going to
master clock control.
Setting this bit converts SHIP_ID from default to the other
(0xBA/0xBB => 0x90/0x91).
When set, a forced restart occurs when a bad frame is detected.
This can shorten the delay when waiting for a good frame
because the delay when masking out a bad frame is the
integration time rather than the full frame time.
0: Only output good frames (default)
A bad frame is defined as the first frame following a change to:
window size or position, horizontal blanking, pixel clock speed,
zoom, row or column skip, or mirroring.
1: Output all frames (including bad frames)
Setting this bit stops ST ANDBY from affecting entry to or exit
from the low-power state.
By default, asserting STANDBY causes the ball interface to enter
High-Z. Setting this bit stops ST ANDBY from contributing to
output enable control.
DESCRIPTION
38
SOC VGA DIGITAL IMAGE SENSOR
Micron Technology, Inc., reserves the right to change products or specificat ions wit hout not ice.
DEFAULT
(HEX)
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
SYNC’D TO
FRAME
START
©2004 Micron Technology, Inc. All rights reserved.
N
Y
Y
Y
N
N
N
N
N
N
PRELIMINARY
MT9V112
FRAME
BAD
YM
N
N
0
0
0
0
0
0
0
WRITE
READ/
W
W
W
W
W
W
W
W
W
W