mt9v011p11st Micron Semiconductor Products, mt9v011p11st Datasheet - Page 11

• Manufacturer Part Number: mt9v011p11st
• Description: 1/4-inch Vga Cmos Active-pixel Digital Image Sensor
• Manufacturer: Micron Semiconductor Products

Serial Bus Description
through the two-wire serial interface bus. The sensor is
a serial interface slave and is controlled by the serial
clock (SCLK), which is driven by the serial interface
master. Data is transferred into and out through the
MT9V011 serial data (SDATA ) line. The SDATA line is
pulled up to V
the slave or master device can pull the SDA TA line
down—the serial interface protocol determines which
device is allowed to pull the SDA TA line down at any
given time. The registers are 16 bits wide, and can be
accessed through 16- or eight-bit two-wire serial bus
sequences.
Protocol
ent transmission codes, as follows:
• a start bit
• the slave device eight-bit address
• a(n) (no) acknowledge bit
• an eight-bit message
• a stop bit
Sequence
ter sending a start bit. After the start bit, the master
sends the slave device’ s eight-bit address. The last bit
of the address determines if the request will be a read
or a write, where a “0” indicates a write and a “1” indi-
cates a read. The slave device acknowledges its address
by sending an acknowledge bit back to the master.
the eight-bit register address to which a write should
take place. The slave sends an acknowledge bit to indi-
cate that the register address has been received. The
master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each eight
bits. The MT9V011 uses 16-bit data for its internal reg-
isters, thus requiring two eight-bit transfers to write to
one register. After 16 bits are transferred, the register
address is automatically incremented, so that the next
16 bits are written to the next register address. The
master stops writing by sending a start or stop bit.
the master sends the write-mode slave address and
eight-bit register address, just as in the write request.
The master then sends a start bit and the read-mode
slave address. The master then clocks out the register
data eight bits at a time. The master sends an acknowl-
09005aef80c6407f
MT9V011_external_DS_2.fm - Rev. A 8/04 EN
Registers are written to and read from the MT9V 011
The two-wire serial interface defines several differ-
A typical read or write sequence begins by the mas-
If the request was a write, the master then transfers
A typical read sequence is executed as follows. First
DD
off-chip by a 1.5KΩ resistor. Either
11
1/4-INCH VGA CMOS ACTIVE-PIXEL
edge bit after each eight-bit transfer. The register
address is auto-incremented after every 16 bits is
transferred. The data transfer is stopped when the
master sends a no-acknowledge bit. The MT9V011
allows for eight-bit data transfers through the two-wire
serial interface by writing (or reading) the most signifi-
cant eight bits to the register and then writing (or read-
ing) the least significant eight bits to Reg0x80 (128).
Bus Idle State
are HIGH. Control of the bus is initiated with a start
bit, and the bus is released with a stop bit. Only the
master can generate the start and stop bits.
Start Bit
of the data line while the clock line is HIGH.
Stop Bit
of the data line while the clock line is HIGH.
Slave Address
device consists of seven bits of address and 1 bit of
direction. A “0” in the LSB of the address indicates
write mode, and a “1” indicates read mode. The write
address of the sensor is 0xBA , while the read address is
0xBB.
Data Bit Transfer
The two-wire serial interface clock pulse is provided by
the master. The data must be stable during the HIGH
period of the serial clock—it can only change when the
two-wire serial interface clock is LOW . Data is trans-
ferred eight bits at a time, followed by an acknowledge
bit.
Acknowledge Bit
The transmitter (which is the master when writing, or
the slave when reading) releases the data line, and the
receiver indicates an acknowledge bit by pulling the
data line low during the acknowledge clock pulse.
The bus is idle when both the data and clock lines
The start bit is defined as a HIGH-to-LOW transition
The stop bit is defined as a LOW -to-HIGH transition
The eight-bit address of a two-wire serial interface
One data bit is transferred during each clock pulse.
The master generates the acknowledge clock pulse.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DIGITAL IMAGE SENSOR
©2004 Micron Technology, Inc.
Preliminary