mt9v034c12stmdes aptina, mt9v034c12stmdes Datasheet - Page 75

• Manufacturer Part Number: mt9v034c12stmdes
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Propagation Delays for PIXCLK and Data Out Signals
Figure 36:
Propagation Delays for FRAME_VALID and LINE_VALID Signals
Figure 37:
PDF: 09005aef8366edcb/Source: 09005aef8366ede5
MT9V034_DS - Rev. A 10/08 EN
Propagation Delays for PIXCLK and Data Out Signals
Propagation Delays for FRAME_VALID and LINE_VALID Signals
The pixel clock is inverted and delayed relative to the master clock. The relative delay
from the master clock (SYSCLK) rising edge to both the pixel clock (PIXCLK) falling edge
and the data output transition is typically 7ns. Note that the falling edge of the pixel
clock occurs at approximately the same time as the data output transitions. See Table 19
for data setup and hold times.
The LV and FV signals change on the same rising master clock edge as the data output.
The LV goes HIGH on the same rising master clock edge as the output of the first valid
pixel's data and returns LOW on the same master clock rising edge as the end of the
output of the last valid pixel's data.
As shown in the “Output Data Timing” on page 13, FV goes HIGH 143 pixel clocks before
the first LV goes HIGH. It returns LOW 23 pixel clocks after the last LV goes LOW.
FRAME_VALID
D
OUT
SYSCLK
PIXCLK
LINE_VALID
(9:0)
PIXCLK
t
PD
Aptina Confidential and Proprietary
t
PLH
t
P
FLR
t
P
SD
t
F
75
FRAME_VALID
MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor
LINE_VALID
t
HD
PIXCLK
t
R
Aptina Imaging reserves the right to change products or specifications without notice.
t
P
FLF
©2008 Aptina Imaging Corporation. All rights reserved.
Electrical Specifications