mt9v034c12stmdes aptina, mt9v034c12stmdes Datasheet - Page 14

• Manufacturer Part Number: mt9v034c12stmdes
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Table 4:
Table 5:
PDF: 09005aef8366edcb/Source: 09005aef8366ede5
MT9V034_DS - Rev. A 10/08 EN
Parameter
Nrows x (A + Q)
Parameter
V’
F
A+Q
V
F
Frame Time (continued)
Frame Time—Long Integration Time
Name
Vertical blanking (long
integration time)
Total frame time (long
integration time)
Notes:
Name
Row time
Vertical blanking
Frame valid time
Total frame time
Sensor timing is shown above in terms of pixel clock and master clock cycles (refer to
Figure 7 on page 13). The recommended master clock frequency is 26.66 MHz. The
vertical blanking and the total frame time equations assume that the integration time
(Coarse Shutter Width plus Fine Shutter Width) is less than the number of active rows
plus the blanking rows minus the overhead rows:
If this is not the case, the number of integration rows must be used instead to determine
the frame time, as shown in Table 5. In this example it is assumed that the Coarse Shutter
Width Control is programmed with 523 rows, and the Fine Shutter Width Total is zero.
For Simultaneous mode, if the exposure time registers (Coarse Shutter Width Total plus
Fine Shutter Width Total) exceed the total readout time, then the vertical blanking time
is internally extended automatically to adjust for the additional integration time
required. This extended value is not written back to the vertical blanking registers. The
Vertical Blank register can be used to adjust frame-to-frame readout time. This register
does not affect the exposure time but it may extend the readout time.
1. The MT9V034 uses column parallel analog-digital converters, thus short row timing is not possible.
The minimum total row time is 690 columns (horizontal width + horizontal blanking). The mini-
mum horizontal blanking is 61. When the window width is set below 627, horizontal blanking
must be increased.
Window Height + Vertical Blanking – 2
Equation
(Number of Master Clock Cycles)
Context A: (R0x0B + 2 - R0x03) × (A + Q) + R0xD5 + 4
Context B: (R0xD2 + 2 - R0xCB) x (A + Q) + R0xD8 + 4
Context A: (R0x0B + 2) × (A + Q) + R0xD5 + 4
Context B: (R0xD2 + 2) x (A + Q) + R0xD8 + 4
Aptina Confidential and Proprietary
Equation
Context A: (R0x03) × (A + Q)
V + (Nrows x (A + Q))
Context A: R0x04 + R0x05
Context B: R0xCC + R0xCD
Context A: (R0x06) x (A + Q) + 4
Context B: (R0xCE) x (A + Q) + 4
Context B: (R0xCB) x (A + Q)
14
MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor
Aptina Imaging reserves the right to change products or specifications without notice.
Default Timing at 26.66 MHz
444,154 pixel clocks
846 pixel clocks
= 846 master
= 31.72μs
38,074 pixel clocks
= 38,074 master
= 1.43ms
406,080 pixel clocks
= 406,080 master
= 15.23ms
= 444,154 master
= 16.66ms
©2008 Aptina Imaging Corporation. All rights reserved.
Default Timing
at 26.66 MHz
38,074 pixel clocks
= 38,074 master
= 1.43ms
444,154 pixel clocks
= 444,154 master
= 16.66ms
Output Data Format
(EQ 1)