m470l6423en0-cb3 Samsung Semiconductor, Inc., m470l6423en0-cb3 Datasheet - Page 3
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m470l6423en0-cb3
Manufacturer Part Number
m470l6423en0-cb3
Description
512mb Unbuffered Sodimm Based On Stsop
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.M470L6423EN0-CB3.pdf
(13 pages)
200Pin Unbuffered SODIMM based on 256Mb E-die (x8)
Ordering Information
Operating Frequencies
Feature
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil), double (512MB) sided
•
• 54pin sTSOP(II)-300 package
512MB Unbuffered SODIMM(based on sTSOP)
SSTL_2 Interface
M470L6423EN0-C(L)B3/A2/B0
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Part Number
B3(DDR333@CL=2.5)
133MHz
166MHz
2.5-3-3
Density
512MB
Organization
64M x 64
A2(DDR266@CL=2)
133MHz
133MHz
2-3-3
32Mx8 (K4H560838E) * 16EA
Component Composition
Rev. 1.3 March. 2004
B0(DDR266@CL=2.5)
DDR SDRAM
100MHz
133MHz
2.5-3-3
1,250mil
Height