m470l3224dt0 Samsung Semiconductor, Inc., m470l3224dt0 Datasheet - Page 8

• Manufacturer Part Number: m470l3224dt0
• Description: 256mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

M470L3224DT0
AC Timming Parameters & Specifications
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
Output Slew Rate Matching Ratio(rise to fall)
Parameter
CL=2.0
CL=2.5
Symbol
tDQSCK
tWPRES
tDQSQ
tWPRE
tSL(IO)
tDQSS
tDQSH
tRPRE
tRPST
tDQSL
tSL(O)
tSLMR
tWTR
tRCD
tRRD
tCCD
tDSH
tDSC
tSL(I)
tRFC
tRAS
tDSS
tWR
tRC
tRP
tCK
tCH
tAC
tCL
tHZ
tLZ
tIS
tIH
tIS
tIH
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.75
0.75
0.67
-0.6
-0.7
-0.7
-0.7
7.5
0.9
0.4
0.2
0.2
0.9
0.8
0.8
0.5
0.5
1.0
60
72
42
18
18
12
15
(DDR333)
1
1
6
0
-
-TCB3
Max
0.55
0.55
+0.6
+0.7
0.45
1.25
+0.7
+0.7
70K
1.1
0.6
1.1
4.5
1.5
12
12
-0.75
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
(DDR266A)
7.5
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
0.5
0.5
1.0
65
75
45
20
20
15
15
1
1
0
-
-TCA2
200pin DDR SDRAM SODIMM
+0.75
+0.75
120K
Max
+0.75
+0.75
0.55
0.55
1.25
0.5
1.1
0.6
1.1
4.5
1.5
12
12
-0.75
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
(DDR266B)
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
0.5
0.5
1.0
65
75
45
20
20
15
15
10
1
1
0
-
-TCB0
+0.75
+0.75
120K
Max
+0.75
+0.75
0.55
0.55
1.25
0.5
1.1
0.6
1.1
4.5
1.5
12
12
Rev. 0.1 Jan. 2002
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
-0.8
-0.8
0.9
0.4
0.2
0.2
0.9
1.1
1.1
1.1
1.1
-0.8
-0.8
0.5
0.5
1.0
70
80
48
20
20
15
15
10
1
1
0
(DDR200)
-
-TCA0
120K
Max
0.55
0.55
+0.8
+0.8
1.25
+0.8
+0.8
0.6
1.1
0.6
1.1
4.5
1.5
12
Unit Note
V/ns
V/ns
V/ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
5
5
5
2
6
6
6
6
6
7