m470l3224dt0 Samsung Semiconductor, Inc., m470l3224dt0 Datasheet - Page 6

• Manufacturer Part Number: m470l3224dt0
• Description: 256mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
AC OPERATING TEST CONDITIONS
DDR SDRAM IDD spec table
M470L3224DT0
AC Operating Conditions
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
IDD6
Input reference voltage for Clock
Input signal maximum peak swing
Input Levels(V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
2. The value of V
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Symbol
IDD4W
IDD2Q
IDD2P
IDD3P
IDD3N
IDD4R
IDD7A
IDD2F
IDD0
IDD1
IDD5
Low power
Normal
IH
Parameter/Condition
/V
IX
IL
is expected to equal 0.5*V
Parameter
)
B3(DDR333@CL=2.5)
1020
1620
580
720
200
160
280
440
980
940
24
24
12
DDQ
(V
DD
of the transmitting device and must track variations in the DC level of the same.
B0(DDR266@CL=2.5)
A2(DDR266@CL=2)
=2.5V, V
1380
500
640
160
144
240
360
860
800
840
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
24
24
12
DDQ
=2.5V, T
V
REF
See Load Circuit
VREF + 0.31
0.7
0.5*VDDQ-0.2
+0.31/V
0.5 * V
200pin DDR SDRAM SODIMM
Value
V
A
1.5
V
= 0 to 70
REF
Min
tt
DDQ
REF
A0(DDR200@CL=2)
-0.31
C
)
0.5*VDDQ+0.2
1200
460
580
144
128
200
320
760
680
760
VREF - 0.31
24
24
12
VDDQ+0.6
Max
Rev. 0.1 Jan. 2002
Unit
V
V
V
V
V
Unit
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
Optional
Note
Notes
Note
3
3
1
2