m393b1k70bh1 Samsung Semiconductor, Inc., m393b1k70bh1 Datasheet - Page 11

• Manufacturer Part Number: m393b1k70bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

10.0 Functional Block Diagram:
Registered DIMM
DM8/DQS17
DM3/DQS12
DM2/DQS11
DM1/DQS10
DM0/DQS9
DQ[31:24]
DQ[23:16]
V
V
V
V
V
V
Note :
1. DQ-to-I/O wiring may be changed within a byte.
2. Unless otherwise noted, resistor values are 15
3. RS0 and RS1 alternate between the back and front sides of the
DIMM.
4. ZQ resitors are 240
appropriate wiring diagram.
5. See the wiring diagrams for all resistors associated with the command,
address and control bus.
DQ[15:8]
DDSPD
DD
TT
REFCA
REFDQ
SS
DQ[7:0]
CB[7:0]
DQS17
DQS12
DQS11
DQS10
10.1 4GB, 512Mx72 Module
DQS8
DQS8
DQS3
DQS3
DQS2
DQS2
DQS1
DQS1
DQS0
DQS0
DQS9
Vtt
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
Ω ±
D8
D3
D2
D1
D0
1% . For all other resistor values refer to the
Serial PD
D0 - D17
D0 - D17
D0 - D17
D0 - D17
(Populated as 2 rank of x8 DDR3 SDRAMs)
EVENT
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
SCL
Thermal sensor with SPD
D17
D12
D11
D10
D9
Ω ±
EVENT
5%.
SA0 SA1 SA2
A0
A1
DM4/DQS13
DM5/DQS14
DM6/DQS15
DM7/DQS16
A2
DQ[39:32]
DQ[47:40]
DQ[55:48]
DQ[63:56]
DQS13
DQS14
DQS15
DQS16
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
11 of 51
Vtt
SDA
PAR_IN
DQS
DQS
TDQS
TDQS
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
ZQ
ZQ
ZQ
S0*
S1*
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
RESET**
D4
D5
D6
D7
CK0
CK0
*S[3:2], CKE1, ODT1, CK1 and CK1 are NC
RST
QERR
1:2
R
G
R
E
S
T
E
I
DQS
DQS
TDQS
TDQS
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
ZQ
ZQ
ZQ
PST** : SDRAMs D[8:0]
Err_out
Rev. 1.0 December 2008
RS0A-> CS0 : SDRAMs D[3:0], D8
RS0B-> CS0 : SDRAMs D[7:4]
RS1A-> CS1 : SDRAMs D[12:9], D17
RS1B-> CS1 : SDRAMs D[16:13]
RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17
RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]
RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17
RA[N:0]B -> A[N:0] : SDRAMs D[7:4, D[16:13]]
RRASA -> RAS : SDRAMs D[3:0], D[12:8], D17
RRASB -> RAS : SDRAMs D[7:4], D[16:13]
RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17
RCASB -> CAS : SDRAMs D[7:4], D[16:13]
RWEA -> WE : SDRAMs D[3:0], D[12:8], D17
RWEB -> WE : SDRAMs D[7:4], D[16:13]
RCKE0A -> CKE0 : SDRAMs D[3:0], D8
RCKE0B -> CKE0 : SDRAMs D[7:4]
RCKE1A -> CKE1 : SDRAMs D[12:9], D17
RCKE1B -> CKE1 : SDRAMs D[16:13]
RODT0A -> ODT0 : SDRAMs D[3:0], D8
RODT0B -> ODT0 : SDRAMs D[7:4]
RODT1A -> ODT1 : SDRAMs D[12:9], D17
RODT1A -> ODT1 : SDRAMs D[16:13]
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0B -> CK : SDRAMs D[7:4]
PCK1A -> CK : SDRAMs D[12:9], D17
PCK1B -> CK : SDRAMs D[16:13]
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0B -> CK : SDRAMs D[7:4]
PCK1A -> CK : SDRAMs D[12:9], D17
PCK1B -> CK : SDRAMs D[16:13]
D13
D14
D15
D16
DDR3 SDRAM