mt9htf12872py-53e Micron Semiconductor Products, mt9htf12872py-53e Datasheet - Page 8

• Manufacturer Part Number: mt9htf12872py-53e
• Description: 256mb, 512mb, 1gb X72, Ecc, Sr 240-pin Ddr2 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

General Description
Register and PLL Operation
Serial Presence-Detect Operation
PDF: 09005aef82250868/Source: 09005aef82250815
HTF9C32_64_128x72.fm - Rev. E 6/08 EN
The MT9HTF3272, MT9HTF6472(P), and MT9HTF12872(P) DDR2 SDRAM modules are
high-speed, CMOS, dynamic random-access 256MB, 512MB, and 1GB memory modules
organized in x72 configurations. These DDR2 SDRAM modules use internally configured
4-bank (256Mb, 512Mb) or 8-bank (1Gb) DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single
4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
DDR2 SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM
devices on the following rising clock edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL) on the module receives and redrives the differential clock signals
(CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address,
command, control, and clock signal loading by isolating DRAM from the system
controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the
JEDEC clock reference board. Registered mode will add one clock cycle to CL.
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various SDRAM organizations and timing parameters. The remaining 128 bytes
of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I
which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected
to V
2
C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0],
SS
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
, permanently disabling hardware write protect.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2003 Micron Technology, Inc. All rights reserved.