mt9htf12872py-53e Micron Semiconductor Products, mt9htf12872py-53e Datasheet - Page 10

• Manufacturer Part Number: mt9htf12872py-53e
• Description: 256mb, 512mb, 1gb X72, Ecc, Sr 240-pin Ddr2 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

I
Table 10:
PDF: 09005aef82250868/Source: 09005aef82250815
HTF9C32_64_128x72.fm - Rev. E 6/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads, I
t
commands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads, I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
DD
RC =
RCD =
CK =
RAS =
RP =
RAS =
CK =
Specifications
t
t
t
t
RP (I
RC (I
CK (I
CK (I
t
t
OUT
OUT
t
RAS MAX (I
RAS MAX (I
RCD (I
DD
DD
= 0mA; BL = 4, CL = CL (I
DD
DD
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
DDR2 I
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus
),
DD
t
t
RAS =
RC =
); CKE is HIGH, S# is HIGH between valid commands; Address
DD
DD
t
t
),
),
CK =
DD
RC (I
t
RAS MIN (I
t
t
DD
t
RP =
RP =
CK =
Specifications and Conditions – 256MB
), AL = 0;
DD
t
CK (I
),
t
t
t
RP (I
RP (I
CK (I
t
RRD =
DD
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
DD
DD
DD
),
DD
DD
DD
t
); CKE is HIGH, S# is HIGH between valid
CK =
t
); CKE is HIGH, S# is HIGH between valid
); CKE is HIGH, S# is HIGH between valid
RC =
), AL =
); REFRESH command at every
), AL = 0;
t
RRD (I
t
CK (I
t
RC (I
t
RCD (I
DD
DD
t
),
DD
CK =
),
t
t
DD
RCD =
),
CK =
t
DD
t
RAS =
t
CK =
t
4W
RAS =
CK =
t
) - 1 ×
CK (I
t
CK (I
t
t
t
RCD (I
OUT
CK (I
CK =
t
t
DD
t
CK (I
RAS MAX (I
t
CK =
10
RAS MIN (I
t
CK (I
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
DD
),
= 0mA; BL = 4,
DD
t
),
DD
DD
CK (I
t
),
DD
CK (I
); CKE is
); CKE is
t
);
RFC (I
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
DD
); CKE
);
),
),
DD
)
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
I
I
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
4R
2P
3P
0
1
5
6
7
Electrical Specifications
1,710
1,620
1,620
2,250
-667
810
900
360
360
270
450
45
54
45
©2003 Micron Technology, Inc. All rights reserved.
1,440
1,350
1,530
2,160
-53E
720
810
315
315
225
360
45
54
45
1,125
1,035
1,485
2,070
-40E
675
765
225
270
180
270
45
54
45
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA