mt8vddt6464hg-40b Micron Semiconductor Products, mt8vddt6464hg-40b Datasheet - Page 9

• Manufacturer Part Number: mt8vddt6464hg-40b
• Description: 256mb, 512mb X64, Sr Pc3200 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

Table 6:
NOTE:
Table 7:
pdf: 09005aef80b577e4, source: 09005aef80921669
DDA8C32_64x64HG.fm - Rev. D 9/04 EN
1. For a burst length of two, A1
2. For a burst length of four, A2
3. For a burst length of eight, A3
4. Whenever a boundary of the block is reached within a
5. i = 9, (256MB)
LENGTH
BURST
element block; A0 selects the first access within the
block.
element block; A0
block.
element block; A0
block.
given sequence above, the following access wraps
within the block.
i = 9, 11 (512MB).
SPEED
-40B
2
4
8
A2 A1 A0
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
75
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
CL = 2
f
–
–
A0
CLOCK FREQUENCY (MHZ)
A1 select the first access within the
A2 select the first access within the
0
1
0
1
0
1
0
1
0
1
0
1
0
1
133
ALLOWABLE OPERATING
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
SEQUENTIAL
75
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
ORDER OF ACCESSES
CL = 2.5
–
–
0-1
1-0
Ai select the two-data-
WITHIN A BURST
Ai select the four-data-
–
Ai select the eight-data-
f
167
INTERLEAVED
133
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
CL = 3
0-1
1-0
f
200
9
reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Extended Mode Register
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram, on page 10. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
COMMAND
COMMAND
COMMAND
256MB, 512MB (x64, SR) PC3200
All other combinations of values for A7–A12 are
The extended mode register controls functions
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
CK
CK
CK
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
READ
READ
READ
T0
T0
T0
200-PIN DDR SODIMM
TRANSITIONING DATA
CL = 2
CL = 2.5
NOP
NOP
NOP
T1
T1
T1
CL = 3
T2
NOP
NOP
NOP
T2
T2
©2004 Micron Technology, Inc.
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T2n
T2n
T2n
T3
NOP
NOP
NOP
T3
T3
T3n
T3n
T3n