mt8vddt3264hg-265 Micron Semiconductor Products, mt8vddt3264hg-265 Datasheet - Page 5

• Manufacturer Part Number: mt8vddt3264hg-265
• Description: 128mb, 256mb, 512mb X64, Sr 200-pin Ddr Sdram Sodimm
• Manufacturer: Micron Semiconductor Products

Table 7:
PDF: 09005aef8092973f/Source: 09005aef80921669
DD8C16_32_64x64H.fm - Rev. C 10/07 EN
RAS#, CAS#, WE#
DQS0–DQS7
DQ0–DQ63
CK0, CK0#,
DM0–DM7
CK1, CK1#
BA0, BA1
SA0–SA2
Symbol
A0–A12
V
CKE0
Pin Descriptions
SDA
DDSPD
V
V
S0#
SCL
V
NC
REF
DD
SS
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
128MB, 256MB, 512MB (x64, SR) 200-Pin DDR SDRAM SODIMM
I/O
I/O
I/O
–
Description
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command. A0–A11 (128MB) and A0–A12 (256MB, 512MB).
Bank address: BA0 and BA1 define the device bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal
clock, input buffers, and output drivers.
Data write mask: DM LOW enables WRITE operation. DM HIGH blocks WRITE
operation. DM lines do not affect READ operation.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when S# is registered HIGH. S# is
considered part of the command code.
Presence-detect address inputs: These pins are used to configure the
presence-detect device.
Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
Data I/Os: Data bus.
Data strobe: Output with read data, input with write data. DQS is edge-
aligned with read data, center-aligned with write data. Used to capture data.
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
Serial EEPROM positive power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (V
Ground.
No connect: These pins are not connected on the module.
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
/2).
Pin Assignments and Descriptions
©2004 Micron Technology, Inc. All rights reserved.