mt18hvf25672py-53e Micron Semiconductor Products, mt18hvf25672py-53e Datasheet - Page 9
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mt18hvf25672py-53e
Manufacturer Part Number
mt18hvf25672py-53e
Description
1gb, 2gb X72, Ecc, Sr 240-pin Ddr2 Vlp Rdimm
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT18HVF25672PY-53E.pdf
(16 pages)
Table 10:
PDF: 09005aef827840fc/Source: 09005aef826fd98c
HVF18C128_256x72.fm - Rev. A 3/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
MIN (I
commands; Address bus inputs are switching; Data pattern is same as
I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; I
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current:
t
Other control and address bus inputs are switching; Data bus inputs are
switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
DD
RC =
CK =
RAS =
RAS =
RFC (I
CK =
DD
4W
),
t
t
t
t
DD
DD
RC (I
CK (I
RP =
CK (I
t
t
OUT
OUT
RAS MAX (I
RAS MAX (I
),
) interval; CKE is HIGH, S# is HIGH between valid commands;
t
DD
DD
RCD =
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
RP (I
),
); CKE is LOW; Other control and address bus
DDR2 I
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the
1Gb (256 Meg x 4) component data sheet
),
t
t
RAS =
RC =
DD
DD
t
RCD (I
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
t
),
),
RC (I
DD
t
RAS MIN (I
t
t
RP =
RP =
t
DD
CK =
Specifications and Conditions – 2GB
DD
); CKE is HIGH, S# is HIGH between valid
t
),
CK =
DD
t
t
RP (I
RP (I
t
t
CK (I
RRD =
), AL = 0;
DD
t
DD
DD
CK (I
DD
DD
DD
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
t
), AL = 0;
); REFRESH command at every
), AL =
RRD (I
DD
t
CK =
),
t
DD
RC =
t
RCD (I
t
CK (I
),
t
CK =
t
RCD =
t
t
RC (I
CK =
t
DD
DD
t
CK =
CK =
1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
t
CK (I
),
) - 1 x
DD
t
t
CK (I
t
RAS =
RCD (I
t
),
t
t
OUT
CK (I
CK =
t
CK (I
DD
CK =
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
RAS =
t
9
DD
),
CK (I
= 0mA;
DD
DD
DD
t
t
),
RAS MAX
CK (I
t
CK (I
),
); CKE is
); CKE is
DD
t
RAS
);
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
);
);
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
I
I
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
1,620
1,980
1,080
2,880
2,880
4,230
6,030
-80E
-800
126
900
900
720
180
126
1,530 1,260 1,260
1,800 1,710 1,620
2,430 2,250 1,890
2,430 2,250 1,890
3,870 3,780 3,690
5,040 4,860 4,680
©2007 Micron Technology, Inc. All rights reserved.
-667
126
720
720
540
180
990
126
I
DD
-53E
126
720
720
540
180
810
126
Specifications
-40E Units
126
630
630
540
180
720
126
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA