mt18hvf25672py-53e Micron Semiconductor Products, mt18hvf25672py-53e Datasheet - Page 8

• Manufacturer Part Number: mt18hvf25672py-53e
• Description: 1gb, 2gb X72, Ecc, Sr 240-pin Ddr2 Vlp Rdimm
• Manufacturer: Micron Semiconductor Products

I
Table 9:
PDF: 09005aef827840fc/Source: 09005aef826fd98c
HVF18C128_256x72.fm - Rev. A 3/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
t
switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge standby current: All device banks idle;
Other control and address bus inputs are switching; Data bus inputs are switching
Active power-down current: All device banks open;
t
stable; Data bus inputs are floating
Active standby current: All device banks open;
t
bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
t
switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads,
I
(I
Data bus inputs are switching
Burst refresh current:
is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are
switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads,
I
(I
commands; Address bus inputs are stable during deselects; Data bus inputs are switching
DD
OUT
OUT
RC =
RCD =
CK =
RP =
RP =
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
),
Specifications
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
t
t
t
t
RP (I
RP (I
RC (I
RRD =
CK (I
t
RCD (I
DD
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Other control and address
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
),
DDR2 I
Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the
512Mb (128 Meg x 4) component data sheet
); CKE is LOW; Other control and address bus inputs are
RRD (I
DD
t
RAS =
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
DD
), AL = 0;
), AL = 0;
DD
DD
),
t
RAS MIN (I
t
t
CK =
RCD =
Specifications and Conditions – 1GB
t
t
DD
DD
CK =
CK =
t
CK (I
), AL = 0;
), AL =
t
RCD (I
DD
t
t
CK (I
CK (I
DD
DD
); CKE is HIGH, S# is HIGH between valid commands;
4W
); REFRESH command at every
DD
t
RCD (I
DD
DD
t
); CKE is HIGH, S# is HIGH between valid
CK =
),
),
t
t
RC =
RAS =
DD
t
CK (I
) - 1 x
t
t
RC (I
CK =
t
t
t
RAS MAX (I
DD
CK =
CK =
1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
t
CK (I
),
DD
t
CK (I
t
t
RAS =
t
),
t
OUT
CK =
CK (I
t
CK (I
CK =
DD
t
RAS =
8
DD
);
= 0mA;
DD
t
DD
DD
CK (I
),
t
t
t
CK =
RAS MAX (I
CK (I
),
); CKE is HIGH, S# is HIGH;
t
),
RAS =
t
RAS MIN (I
t
DD
RFC (I
DD
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CK (I
); CKE is LOW; Other
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
); CKE is HIGH, S# is
t
RAS MAX (I
DD
DD
DD
) interval; CKE
),
DD
),
t
RC =
t
),
RP =
DD
t
RC
t
RP
),
Symbol
I
©2007 Micron Technology, Inc. All rights reserved.
I
I
I
I
I
I
DD
DD
DD
DD
DD
I
I
DD
DD
I
I
I
DD
DD
DD
DD
DD
I
4W
2Q
2N
3N
4R
2P
3P
DD
0
1
5
6
7
Specifications
1,800
2,070
1,260
3,510
3,690
4,140
5,400
-80E
-800
126
900
990
720
216
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA