mt18hts25672chy-667 Micron Semiconductor Products, mt18hts25672chy-667 Datasheet - Page 8

• Manufacturer Part Number: mt18hts25672chy-667
• Description: 2gb, 4gb X72, Dr 200-pin Ddr2 Sdram Socdimm
• Manufacturer: Micron Semiconductor Products

Table 9:
PDF: 09005aef8253e3ea/Source: 09005aef8253e404
HTS18C256_512x72CH.fm - Rev. B 6/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All device banks open;
t
are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus inputs are
switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads;
I
t
are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads;
I
t
valid commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
RAS =
RCD =
CK =
RAS =
OUT
RP =
OUT
RC =
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
t
t
RP (I
RC (I
CK (I
t
t
t
RAS MIN (I
RAS MAX (I
RCD (I
DD
DD
DD
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
); CKE is LOW; Other control and address bus inputs
DDR2 I
Values shown are for MT47H256M8THN DDR2 TwinDie SDRAM components from device I
2Gb TwinDie (256 Meg x 8) component data sheet
DD
t
RRD =
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
), AL = 0;
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
t
CK =
),
DD
t
RRD (I
t
RP =
t
CK =
Specifications and Conditions – 2GB
t
CK (I
t
CK =
DD
DD
t
DD
RP (I
t
CK (I
), AL = 0;
), AL =
),
DD
t
t
DD
RCD =
),
CK (I
DD
t
); CKE is HIGH, S# is HIGH between valid
RC =
); REFRESH command at every
t
RCD (I
DD
t
t
CK =
RCD (I
),
t
RC (I
t
RAS =
DD
DD
t
CK (I
DD
) - 1 ×
DD
4W
t
),
); CKE is HIGH, S# is HIGH between
CK =
2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM
t
t
RAS MAX (I
DD
t
t
CK =
RAS =
CK =
t
),
CK (I
t
CK (I
t
RAS =
t
t
OUT
CK =
t
CK (I
CK (I
t
t
DD
CK =
RAS MIN (I
8
DD
);
= 0mA; BL = 4,
DD
t
DD
DD
),
t
t
CK (I
RAS MAX (I
CK =
t
),
CK (I
); CKE is HIGH, S# is
),
t
t
RC =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
RP =
DD
t
RFC (I
t
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CK (I
DD
); CKE is LOW;
); CKE is
t
),
t
RC (I
RP (I
DD
DD
DD
)
),
DD
),
DD
),
);
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
Electrical Specifications
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
©2006 Micron Technology, Inc. All rights reserved.
1,008
1,323
1,323
2,043
2,628
-667
873
126
423
468
333
153
603
126
DD
values in the
1,233
1,233
1,998
2,538
-53E
738
963
126
423
468
333
153
513
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA