mt18htf6472ay Micron Semiconductor Products, mt18htf6472ay Datasheet - Page 11

• Manufacturer Part Number: mt18htf6472ay
• Description: Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

I
Table 11: DDR2 I
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8)
component data sheet
PDF: 09005aef80e8ad4d
htf18c64_128_256_512x72ay – Rev. I 3/10 EN
Parameter
Operating one bank active-precharge current:
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
= CL (I
t
puts are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
Precharge quiet standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
Active power-down current: All device banks open;
t
stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
DD
RCD (I
CK (I
RP (I
OUT
RP =
DD
),
= 0mA; BL = 4, CL = CL (I
DD
DD
Specifications
t
t
RAS =
DD
RP (I
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
); CKE is LOW; Other control and address bus inputs are
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
),
DD
t
RP =
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus
RAS MIN (I
t
RP (I
t
CK =
DD
DD
Specifications and Conditions – 512MB
DD
DD
t
t
); CKE is HIGH, S# is HIGH between valid commands;
CK (I
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
t
CK (I
512MB, 1GB, 2GB, 4GB (x72, DR) 240-Pin DDR2 SDRAM UDIMM
), AL = 0;
),
t
RC =
DD
t
CK =
); REFRESH command at every
t
RC (I
t
CK =
t
CK (I
DD4W
DD
t
),
DD
CK (I
t
),
RAS =
t
CK =
t
t
RAS =
CK =
DD
t
CK =
),
t
t
CK =
t
t
RAS MIN (I
CK (I
RAS =
t
CK (I
t
OUT
t
CK =
t
RAS MAX (I
t
CK (I
CK =
11
DD
= 0mA; BL = 4, CL
DD
t
),
t
DD
RAS MAX (I
CK (I
),
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
t
CK (I
); CKE is
RAS =
t
DD
RC =
t
RFC (I
DD
),
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
); CKE is
RCD =
t
t
),
); CKE
RC
RAS
DD
t
RP =
DD
)
),
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
1
1
2
2
2
2
1
2
2
2
1
-667
1755
1665
3240
855
945
720
720
540
108
900
90
90
© 2003 Micron Technology, Inc. All rights reserved.
I
DD
-53E
1485
1395
3060
765
855
630
630
450
108
720
90
90
Specifications
1170
1080
2970
-40E
720
810
450
540
360
108
540
90
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA