hb286008c2 HITACHI, hb286008c2 Datasheet - Page 56
![no-image](/images/manufacturer_photos/0/3/301/hitachi_sml.jpg)
hb286008c2
Manufacturer Part Number
hb286008c2
Description
Mega Byte Compactflash
Manufacturer
HITACHI
Datasheet
1.HB286008C2.pdf
(59 pages)
- Current page: 56 of 59
- Download datasheet (203Kb)
HB286008C2, HB286015C2, HB286030C2
True IDE Mode access write AC characteristics
Parameter
Data setup before IOWR
data hold following IOWR
IORD width time
address setup before IOWR
address hold following IOWR
CE setup before IOWR
CE hold following IOWR
IOIS16 delay falling from address
IOIS16 delay rising from address
True IDE Mode access write timing
Attention for Card Use
56
In the reset or power off, all register informations are cleared.
All card status are cleared automatically when Vcc voltage turns below about 2.5V.
After the card hard reset, soft reset, or power on reset, the card cannot access during +RDY/-BSY pin is
"low" level.
Please notice that the card insertion/removal should be executed after card internal operations completed
(status register bit 7 turns from "1" to "0").
-CE2/-CE1
D0 to D15
A0 to A2
-IOIS16
-IOWR
t
drlOIS(ADR)
Symbol
tsu(IOWR)
th(IOWR)
tw(IOWR)
tsuA(IOWR)
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
tdfIOIS16(ADR)
tdfIOIS16(ADR)
t
t
suA(IORD)
suCE(IORD)
-IORD: High Fix, -OE: Low Fix, -WE: High Fix
t
w(IORD)
Min
60
30
165
70
20
5
20
—
—
t
hCE(IORD)
t
t
hA(IORD)
d(IOWR)
Valid Output
Typ
—
—
—
—
—
—
—
—
—
t
h(IOWR)
Max
—
—
—
—
—
—
—
35
35
t
drlOIS(ADR)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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