hb286008c2 HITACHI, hb286008c2 Datasheet - Page 5

• Manufacturer Part Number: hb286008c2
• Description: Mega Byte Compactflash
• Manufacturer: HITACHI

HB286008C2, HB286015C2, HB286030C2
Card Pin Explanation
Address bus (A0 to A10: input): Address bus is A0 to A10. A0 is invalid in word mode. A10 is MSB and
A0 is LSB. In True IDE Mode only A0 to A2 are used for selecting the one of eight registers in the Task File,
the remaining address lines should be grounded by the host.
Data bus (D0 to D15: input/output): Data bus is D0 to D15. D0 is the LSB of the Even Byte of the Word.
D8 is the LSB of the Odd Byte of the Word.
Card enable (-CE1, -CE2: input): -CE1 and -CE2 are low active card select signals. Even addresses are
controlled by -CE1 and odd addresses are by -CE2. In True IDE Mode -CE2 is used for select the Alternate
Status Register and the Device Control Register while -CE1 is the chip select for the other task file registers.
Output enable, ATA select (-OE, -ATASEL: input): -OE is used for the control of read data in Attribute
area or Common memory task file area. To enable True IDE Mode this input should be grounded by the host.
Write enable (-WE: input): -WE is used for the control of data write in Attribute memory area or Common
memory task file area. In True IDE Mode this input signal is not used and should be connected to VCC by
the host.
I/O read (-IORD: input): -IORD is used for control of read data in I/O Task File area. This card dose not
respond to -IORD until I/O card interface setting up.
I/O write (-IOWR: input): -IOWR is used for control of data write in I/O Task File area. This card dose
not respond to -IOWR until I/O card interface setting up.
Ready/Busy, Interrupt request (RDY/-BSY, -IREQ, INTRQ: output): In I/O card mode, this signal is
-IREQ pin. The signal of low level indicates that the card is requesting software service to host, and high
level indicates that the card is not requesting. In memory card mode, the signal is RDY/-BSY pin. RDY/-
BSY pin turns low level during the card internal initialization operation at VCC applied or reset applied, so
next access to the card should be after the signal turned high level. In True IDE Mode signal is the active
high Interrupt Request to the host.
Card detection (-CD1, -CD2: output): -CD1 and -CD2 are the card detection signals. -CD1 and -CD2 are
connected to ground in this card, so host can detect that the card is inserted or not.
Write protect, 16 bit I/O port (WP, -IOIS16: output): In memory card mode, +WP is held low because
this card dose not have write protect switch. In I/O card mode, -IOIS16 is asserted when Task File registers
are accessed in 16bit mode. In True IDE Mode this output signal is asserted low when this device is
expecting a word data transfer cycle.
Attribute memory area selection (-REG: input): -REG should be high level during common memory area
accessing, and low level during Attribute area accessing. Attribute memory area is located only even address,
so D0 to D7 are valid and D8 to D15 are invalid in the word access mode. Odd addresses are invalid in the
byte access mode. In True IDE Mode this input signal is not used and should be connected to VCC.
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