hb286075a1 HITACHI, hb286075a1 Datasheet - Page 4

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hb286075a1

Manufacturer Part Number
hb286075a1
Description
Mega Byte Flash Card
Manufacturer
HITACHI
Datasheet
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
Pin NO.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Card Pin Explanation
Address bus (A0 to A10: input): Address bus is A0 to A10. A0 is invalid in word mode. A10 is MSB and
A0 is LSB.
Data bus (D0 to D15: input/output): Data bus is D0 to D15. D0 is the LSB of the Even Byte of the Word.
D8 is the LSB of the Odd Byte of the Word.
Card enable (-CE1, -CE2: input): -CE1 and -CE2 are low active card select signals. Even addresses are
controlled by -CE1 and odd addresses are by -CE2.
Output enable (-OE: input): -OE is used for the control of data read in Attribute area or Common memory
Task File area.
Write enable (-WE: input): -WE is used for the control of data write in Attribute memory area or Common
memory Task File area.
I/O read (-IORD: input): -IORD is used for control of read data in I/O Task File area. This card dose not
respond to -IORD until I/O card interface setting up.
I/O write (-IOWR: input): -IOWR is used for control of data write in I/O Task File area. This card dose
not respond to -IOWR until I/O card interface setting up.
4
Memory card mode I/O card mode
Signal name I/O
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
+WP
GND
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
Signal name I/O
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
-IOIS16
GND
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
Pin NO.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Memory card mode I/O card mode
Signal name I/O
VS2
+RESET
-WAIT
RFU
-REG
BVD2
BVD1
D8
D9
D10
-CD2
GND
O
I
O
I
O
O
I/O
I/O
I/O
O
Signal name I/O
VS2
+RESET
-WAIT
-INPACK
-REG
-SPKR
-STSCHG
D8
D9
D10
-CD2
GND
O
I
O
O
I
O
O
I/O
I/O
I/O
O

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