lrs1386 Sharp Microelectronics of the Americas, lrs1386 Datasheet - Page 17
![no-image](/images/no-image-200.jpg)
lrs1386
Manufacturer Part Number
lrs1386
Description
Flash Memory
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LRS1386.pdf
(114 pages)
- Current page: 17 of 114
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PCR.15-11 = RESERVED FOR FUTURE
PCR.10-8 = PARTITION CONFIGURATION (PC2-0)
000 = No partitioning. Dual Work is not allowed.
001 = Plane1-3 are merged into one partition.
010 = Plane 0-1 and Plane2-3 are merged into one
100 = Plane 0-2 are merged into one partition.
101 = Plane 1-2 are merged into one partition. There are
011 = Plane 2-3 are merged into one partition. There are
110 = Plane 0-1 are merged into one partition. There are
15
R
R
7
(default in a bottom parameter device)
partition respectively.
(default in a top parameter device)
three partitions in this configuration. Dual work
operation is available between any two partitions.
three partitions in this configuration. Dual work
operation is available between any two partitions.
three partitions in this configuration. Dual work
operation is available between any two partitions.
ENHANCEMENTS (R)
14
R
R
6
13
R
R
5
Partition Configuration Register Definition
Partition Configuration
12
R
R
4
L R S1 3 8 6
PCR.7-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Notes:
1. After power-up or device reset, PCR10-8 (PC2-0) is set
2. See the table below for more details.
3. PCR.15-11 and PCR.7-0 bits are reserved for future use.
111 = There are four partitions in this configuration.
to "001" in a bottom parameter device and "100" in a top
parameter device.
If these bits are read via the Read Identifier Codes/OTP
command, the device may output "1" or "0" on these bits.
11
R
R
3
Each
respectively. Dual work operation is available
between any two partitions.
plane
PC2
10
R
2
corresponds
PC1
R
9
1
to
each
PC0
partition
R
8
0
15
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