s72ns512rd0khfm0 Meet Spansion Inc., s72ns512rd0khfm0 Datasheet - Page 7

• Manufacturer Part Number: s72ns512rd0khfm0
• Description: Mirrorbit Flash Memory And Dram128/256/512 Mb 8/16/32 M X 16 Bit , 1.8 Volt-onlymultiplexed Simultaneous Read/writeburst Mode Flash Memory128/256 Mb 8/16 M X 16 Bit Ddr Dram On Split Bus
• Manufacturer: Meet Spansion Inc.

4.
May 9, 2008 S72NS-R_00_05
Input/Output Descriptions
Amax – A16
ADQ15 – ADQ0
F-CE#
F-OE#
F-WE#
F-VCC
F-VCCQ
F-VSS
F-RDY
F-CLK
F-AVD#
F-RST#
F-ACC
D-A12 – D-A0
D-DQ15 – D-DQ0
D-CLK
D-CE#
D-CKE
D-BA1 – BA0
D-RAS#
D-CAS#
D-UDQM – D-LDQM
D-WE#
D-VSS
D-VSSQ
D-VCCQ
D-VCC
D-UDQS
D-LDQS
D-CLK#
RFU
NC
D-TEST
DNU
D a t a
S h e e t
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Flash Address inputs
Flash multiplexed Address and Data
Flash Chip-enable input.
Flash Output Enable input. Asynchronous relative to CLK for Burst mode.
Flash Write Enable input
Flash device power supply (1.7 V to 1.95 V)
Flash Input/Output Buffer power supply
Flash Ground
Flash ready output. Indicates the status of the Burst read. V
Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates
burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal
address counter. CLK should remain low during asynchronous access.
Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. V
asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising
edge of CLK. V
Flash hardware reset input. V
Flash accelerated input. At V
mode. At V
DRAM Address inputs.
DRAM Data input/output
DRAM System Clock
DRAM Chip Select
DRAM Clock Enable
DRAM Bank Select
DRAM Row Address Strobe
DRAM Column Address Strobe
DRAM Data Input Mask
DRAM Write Enable input
DRAM Ground
DRAM Input/Output Buffer ground
DRAM Input/Output Buffer power supply
DRAM device power supply
DRAM Upper Data Strobe, output with read data and input with write data
DRAM Lower Data Strobe, output with read data and input with write data
DDR Clock for negative edge of CLK
Reserved for Future Use
No Connect. Can be connected to ground or left floating.
Internal Test mode pin for DDR DRAM only. Do not apply any signal on this pin. Can be connected to ground
or left floating.
Do Not Use
( A d v a n c e
IL
, disables all program and erase functions. Should be at V
S72NS-R Based MCPs
IH
= device ignores address inputs
I n f o r m a t i o n )
HH
IL
= device resets and returns to reading array data
, accelerates programming; automatically places device in unlock bypass
OL
= data invalid. V
IH
for all other conditions.
OH
= data valid.
IL
= for
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