am49bds640ah Meet Spansion Inc., am49bds640ah Datasheet - Page 7

• Manufacturer Part Number: am49bds640ah
• Description: Stacked Multichip Package Mcp , Flash Memory And Psram Cmos 1.8 Volt-only Simultaneous Read/write, Burst Mode 64 Megabit 4m ? 16-bit Flash Memory, And 16 Mbit 1m ? 16-bit Psram
• Manufacturer: Meet Spansion Inc.

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 44
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 44
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 45
CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . 45
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Key to Switching Waveforms . . . . . . . . . . . . . . . 46
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 46
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47
December 5, 2003
V
Synchronous/Burst Read ....................................................... 48
CC
Figure 8. Maximum Negative Overshoot Waveform ....................... 44
Figure 9. Maximum Positive Overshoot Waveform......................... 44
Figure 10. Test Setup...................................................................... 46
Table 18. Test Specifications ..........................................................46
Figure 11. Input Waveforms and Measurement Levels .................. 46
Figure 12. V
Figure 13. CLK Synchronous Burst Mode Read (rising active CLK)....
49
Figure 14. CLK Synchronous Burst Mode Read (Falling Active Clock)
49
Figure 15. Synchronous Burst Mode Read..................................... 50
Figure 16. 8-word Linear Burst with Wrap Around.......................... 50
Figure 17. Linear Burst with RDY Set One Cycle Before Data ....... 51
Figure 18. Reduced Wait-state Handshake Burst Suspend/Resume at
an even address.............................................................................. 52
Figure 19. Reduced Wait-state Handshake Burst Suspend/Resume at
an odd address ............................................................................... 52
Figure 20. Reduced Wait-state Handshake Burst Suspend/Resume at
address 3Eh (or offset from 3Eh) .................................................... 53
Figure 21. Reduced Wait-state Handshake Burst SuspendResume at
address 3Fh (or offset from 3Fh by a multiple of 64) ...................... 53
Figure 22. Standard Handshake Burst Suspend prior to Inital Access
54
Figure 23. Standard Handshake Burst Suspend at or after Inital Ac-
cess................................................................................................. 54
Figure 24. Standard Handshake Burst Suspend at address 3Fh (start-
ing address 3Dh or earlier).............................................................. 55
Figure 25. Standard Handshake Burst Suspend at address 3Eh/3Fh
(without a valid Initial Access)......................................................... 55
Figure 26. Standard Handshake Burst Suspend at address 3Eh/3Fh
(with 1 Access CLK)........................................................................ 56
Figure 27. Read Cycle for Continuous Suspend............................. 56
Power-up ......................................................................... 47
CC
Power-up Diagram ................................................. 47
A D V A N C E
Am49BDS640AH
I N F O R M A T I O N
BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 75
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PSRAM DC and Operating Characteristics . . . . 76
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 82
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Asynchronous Mode Read .................................................... 57
Erase/Program Operations ..................................................... 60
Temporary Sector Unprotect .................................................. 69
TLB089—89-ball Fine-Pitch Ball Grid Array (FBGA)
10 x 8 mm Package ................................................................ 81
Figure 28. Asynchronous Mode Read with Latched Addresses .... 58
Figure 29. Asynchronous Mode Read............................................ 58
Figure 30. Reset Timings ............................................................... 59
Figure 31. Asynchronous Program Operation Timings: AVD# Latched
Addresses ...................................................................................... 61
Figure 32. Asynchronous Program Operation Timings: WE# Latched
Addresses ...................................................................................... 62
Figure 33. Synchronous Program Operation Timings: WE# Latched
Addresses ...................................................................................... 63
Figure 34. Synchronous Program Operation Timings: CLK Latched
Addresses ...................................................................................... 64
Figure 35. Chip/Sector Erase Command Sequence ...................... 65
Figure 36. Accelerated Unlock Bypass Programming Timing........ 66
Figure 37. Data# Polling Timings (During Embedded Algorithm) .. 67
Figure 38. Toggle Bit Timings (During Embedded Algorithm)........ 67
Figure 39. Synchronous Data Polling Timings/Toggle Bit Timings 68
Figure 40. DQ2 vs. DQ6................................................................. 68
Figure 41. Temporary Sector Unprotect Timing Diagram .............. 69
Figure 42. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 70
Figure 43. Latency with Boundary Crossing .................................. 71
Figure 44. Latency with Boundary Crossing
into Program/Erase Bank ............................................................... 72
Figure 45. Example of Wait States Insertion.................................. 73
Figure 46. Back-to-Back Read/Write Cycle Timings ...................... 74
Figure 47. Timing of Read Cycle (CE1#s = OE# = VIL, WE# = CE2 =
VIH) ................................................................................................ 78
Figure 48. Timing Waveform of Read Cycle (WE# = VIH) ............. 78
Figure 49. Timing Waveform of Write Cycle (WE# Control............ 79
Figure 50. Timing Waveform of Write Cycle (CE1#s Control, CE2s =
High)............................................................................................... 80
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