am49bds640ah Meet Spansion Inc., am49bds640ah Datasheet - Page 29

• Manufacturer Part Number: am49bds640ah
• Description: Stacked Multichip Package Mcp , Flash Memory And Psram Cmos 1.8 Volt-only Simultaneous Read/write, Burst Mode 64 Megabit 4m ? 16-bit Flash Memory, And 16 Mbit 1m ? 16-bit Psram
• Manufacturer: Meet Spansion Inc.

Notes:
1. Upon power-up or hardware reset, the default setting is
2. RDY will default to being active with data when the Wait
It is recommended that the wait state command
sequence be written, even if the default wait state value
is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default set-
ting.
Reduced Wait-state Handshaking Option
If the device is equipped with the reduced wait-state
handshaking option, the host system should set
address bits A14–A12 to 010 for the system/device to
execute at maximum speed.
Table 11
(wait states) for various conditions.
December 5, 2003
Table 10. Programmable Wait State Settings
seven wait states.
State Setting is set to a total initial access cycle of 2.
A14
0
0
0
0
1
1
1
1
describes the typical number of clock cycles
A13
0
0
1
1
0
0
1
1
A12
0
1
0
1
0
1
0
1
A D V A N C E
Total Initial Access
7 (default)
Reserved
Reserved
Cycles
2
3
4
5
6
Am49BDS640AH
I N F O R M A T I O N
Notes:
1. If the latched address is 3Eh or 3Fh (or an address offset
2. In the 8-, 16-, and 32-word burst modes, the address
3. Typical initial access cycles may vary depending on
Standard Handshaking Option
For optimal burst mode performance on devices with
the standard handshaking option, the host system
must set the appropriate number of wait states in the
flash device depending on the clock frequency.
Table 12
(wait states) for various conditions with A14-A12 set to
101.
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
The autoselect function allows the host system to
determine whether the flash device is enabled for
ha n ds ha ki ng . Se e t h e
Sequence” section on page 29
6
22
28
43
6
28
35
53
Conditions at Address
Initial address
Initial address is 3E or 3Fh (or
offset from these addresses by
a multiple of 64) and is at
boundary crossing*
Table 12. Wait States for Standard Handshaking
Frequency
–
–
Table 11. Wait States for Reduced wait-state
–
–
–
–
–
–
22 MHz
28 MHz
from either address by a multiple of 64), add two access
cycles to the values listed.
pointer does not cross 64-word boundaries (3Fh, or
addresses offset from 3Fh by a multiple of 64).
system margin requirements.
System
Range
28 MHz
43 MHz
54 MHz
35 MHz
53 MHz
66 MHz
describes the typical number of clock cycles
Even Initial
Address
Handshaking
2
2
3
4
2
2
3
4
V
IO
= 1.8 V
“ Aut o se le ct C o mm an d
Odd Initial
Address
Cycles after AVD# Low
for more information.
Typical No. of Clock
2
3
4
5
2
3
4
5
7
7
(54 MHz)
(66 MHz)
Device
Speed
Rating
D
E
27